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Re: Timing inPT
Thanks all,here again I have doubts.
1.What is timing model and what is original.Why P&R tool not using timing models? If we use timing models in P&R tools,then we need not do sign-off ? am I right.
2.We are using same libraries,then how can we say RC delay values and process...
decap leakage
Hi,
Here I have one doubt,is there any rule for puttining decap cells in design? I mean is there any rule that we have to place decap cell in specific distance?
Re: Lib and netlist checks
Hey this is not related to software or application.I am asking about what are checks need to do in logic & physical libs,netlist & sdc and other input files before we start implement the physical design .
Channel between macros
Hi,
Please anybody tell me about how to calculate channel between two macros during floorplan,I mean is there any formula or any calculations.This is depends on technology or depends on design
Thanks in advance.
Hi,
I don't know about power analysis either theorotically & practically.Please if anybody have material or docs regarding static power analysis & dynamic power analysis for different technologies, block & full chip point of view,please upload here and if anybody have practical senarios about...
Lib and netlist checks
Hi,
Before implementing block or full chip we need to some check in given input files.
Please anybody describe detailed about below questions.
1.What are the checks we have to do in given logical libs & physical libs? Please describe detailed about those checks and how...
Re: Full-chip and block
I am not asking about flat level design & hierarchy level design.I am asking about differences between implimentation of full chip and block.Because I worked for block.But I want to know full details about each stage implementation of full chip.
Re: Full-chip and block
Thanks kapil,but I want that during floorplan,placement,cts (clock tree build),Routing,extraction like this at each stage how we implement for full chip & block level.I.e what are the differences (according to implementation) find for fullchip & block.
Regarding this if...
Full-chip and block
Hi,
Please anybody clarify below doubt clearly.
What differences found during implementation of full chip & block level chip.
Thanks in advance.
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