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As the title suggests, please help me understand this. I am not able to find suitable material over the internet on this topic.
In design, I am finding that the IIP3 of a true class AB opamp is worser than a pseudo class AB stage for similar power dissipation.
I have power supply that has channels that look like this
I require 1.8 V from the supply which needs to be connected to the board.
Please suggest any cable/connector with low impedance such that there is minimum fluctuation in VDD/GND during circuit operation.
I have made a mistake in the first post. The first graph shown is the curve of loop gain.
"In case of a single feedback loop, a finite peaking tells you that the circuit is still stable." - Is there any expression or theory for it? I mean, explanation for the peaking after closed loop response...
Dear Dominik, thank you for the reply. I am trying to find the transfer function of output phase vs VCO phase noise of a PLL. I am following Razavi's book on RF Microelectronics.
The open loop transfer function has two poles at zero frequency, and some poles outside the 0dB cutoff frequency of...
I have a feedback circuit whose open loop transfer function characteristic looks as follows
The closed loop transfer function is as follows
If looked closely, the closed loop transfer function exhibits peaking
I want to understand what is causing this peaking. What is its effect? I...
I have a signal cos(w0 * t). It is sampled at frequency f_s. The samples are applied to a moving average filter of length L. I want to find the amplitude of the output.
So far I understand the following. Please do correct me if I am wrong; I am still learning the basics.
DTFT of impulse...
Hello Audioguru, the bandwidth of the op amp is low (less than MHz), I have mentioned only the unity gain bandwidth.
Also as I am creating the op amp with MOS rather than BJT, hence the gain is not large.
The process technology that I am using, provides MOSFETS with high value of Vth, I have...
As I mentioned earlier, the op amp is having 75 dB gain with power supply voltage of 1 V and its slew rate and unity gain bandwidth are as mentioned earlier.
I am not opting for high frequency operation.
Please share some information, if you have any, on resistance values to be decided for...
Hello,
I have a two stage single output opamp. I want to create inverting and noninverting amplifiers and other circuits using the op amp.
How should the choose the resistance values that are connected at the input and feedback?
Opamp specs:
gain 75 dB
phase margin...
Hello Klaus,
Do you think jitter is causing the control voltage variation?
If so, how is jitter manifested in the circuit if the noise is not considered in transient simulation?
After locking, the period of the VCO oscillation at 1000/((N+alpha)fref) time is same as the period at...
Hello KlausST,
I have simulated the PLL without adding noise in any components. The control voltage is still having small variations and is periodic.
Please see-
https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=5556453
The average period of the PLL output will definitely be 166.666ns. But as you know, there will be control voltage fluctuation at the VCO input due the charge pump and frequency divider nonideality. So the individual periods of the multiplied VCO output will not be 166.666ns, but lower and...
I have a rectangular voltage wave of frequency 1 MHz. I need to frequency multiply it to 6 MHz. Is it possible by injection locking?
If any other method for frequency multiplication is possible, please mention.
I thought of creating a PLL, but the control voltage of the PLL has fluctuations in...
Hello, I had a question in op amp?
If we provide equal dc voltages to an op amp it will produce some voltage 'Veq'.
The op amp has a finite gain. My understanding is, if we use this circuit in a negative feedback loop of another circuit X, its input voltages come closer to each other.
However...
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