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Hi nav_vlsi,
The issue solved,the def file have no problem,but some marco/std IO lef files not specified in Star-RCXT command.If all related lef file are specified correctly,Star-RCXT work well.
Thanks for your reply.
Hi all,
I am running DEF/LEF extraction flow using Star-RCXT,and get an ERROR as below:
ERROR: StarXtract
ERROR: Error when parsing DEF file
ERROR: ***/top.def
Warnings:216 Errors:1 (see file readdb.sum)
ReadDB .....
ERROR: StarXtract
ERROR: Read DB Failed (see file...
yes,I created new ctstch file for RESET net,and perform "clockDesign -specfile ...",but CTS failed due to tool don't treat RB pin of FF as syn pin.
so I want to know how to define these RB pin that connect to RESET as syn pin, or if there is other method to hand hign fanout net like RESET?
thanks!
Dear all,
I want to build buffer tree for signal RESET like other clock nets,as so many max_tran vios occurred on this net under bc condition.
I add clock constrainst (skew,latency...) into clock spec file and then do CTS,tool reports that,clock net RESET does not have syn pin,and can not trace...
Hi hanif,
Thanks for your reply!
It seems that Encounter tool can analysis and repaire SI issues by itself.
Could anyone introduce a brief flow or provide a reference case.
Thanks,
david
Question about SI analysis
Dear all,
Can anyone introduce some EDA tools used for SI analysis,including glitch analysis,si delay analysis? and which one is the best choose for the design based on Cadence SOC Encounter,then what about the limitation when using external crosstalk analysis tools...
The problem solved!
There is a bug in the SPACINGTABLE rule definition in the Tech LEF file,after I updated this rule for each metal as below, routing become so easy:
From: SPACINGTABLE PARALLELRUNLENGTH 0 0.5 1.5 WIDTH 0.1 0.1 0.1 0.1 WIDTH 0.5 0.1 0.16 0.16 WIDTH 2.8 0.1 0.16 0.3 ...
Need help on NanoRouter(urgent!!!)
Dear all,
I need your help on routing in NanoRouter,please!
In the past few days,I spend a lot of time on routing,I found a stange scenario shown below.
In the same direction,router always skip at least one track when it routing the next wire (in the same...
Dear Gokhan,
I run P&R in Soc Encounter.
The command setPrerouteAsObs can be used to control standard cell density under power strips.But the 100% via connection from M1 to M6 under wide strip metal still block other nets' routing.I want to know how to control via generation when do special...
How to avoid congestion when adding strips?
Dear all,
In my design, core PG ring and strips were implemented by M6/M7,and strips in vertical orientation is M6.I use default method to connect M6 strips to stand cell connection,M1,the vias from V12,V23,.. to V56 will block the routing of...
I have enabled M6/M7 for routing,but can't improve total overcong and would you please show me an example about what factor of std cell and tech file will effect PNR,thanks a lot.
Dear all,
Please check my design congestion analysis as below,the overcon of ME2 looks very serious,and after global/detail route,the number of DRC vios greater than 5K,
the quality of routing is very bad.my question is
1>why there are so many OverCong in ME2 ? while OverCon of some other...
Dear all,
Could any experts sharing some experience that how to qualify the input design datas for Astro APR.(e.g: Verilog Netlist file, SDC file and other...? ) For example, how can I estimate if all clocks is specified correctly, and timing constraint is defined accurately in SDC file? … thanks
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