Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to avoid congestion when adding stips?

Status
Not open for further replies.

david_zheng

Junior Member level 3
Joined
Aug 19, 2006
Messages
28
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,283
Activity points
1,464
How to avoid congestion when adding strips?

Dear all,

In my design, core PG ring and strips were implemented by M6/M7,and strips in vertical orientation is M6.I use default method to connect M6 strips to stand cell connection,M1,the vias from V12,V23,.. to V56 will block the routing of M2,..M6,it will increase congestion to some extent.I want to know is there any good method to avoid congestion when add strips or connect strips to std cell connection? thanks.

David
 

Hi David,

I don't know which tool you use, however I remember a case from ICC. In Synopsys ICC, there was a command controlling the standard cell utilization under power straps. Using this you can have some sort of channels passing through stacked vias, between standard cells. This limits the detours done because of these stacked vias and allows more uniform cell placement resulting in a reduced congestion.

I hope it is applicable to your design also,

PS: If you're interested, I can check my scripts to find out the exact command to be used.

Best regards,
Gokhan
---
 

Hi David,

I don't know which tool you use, however I remember a case from ICC. In Synopsys ICC, there was a command controlling the standard cell utilization under power straps. Using this you can have some sort of channels passing through stacked vias, between standard cells. This limits the detours done because of these stacked vias and allows more uniform cell placement resulting in a reduced congestion.

I hope it is applicable to your design also,

PS: If you're interested, I can check my scripts to find out the exact command to be used.

Best regards,
Gokhan
---

Dear Gokhan,

I run P&R in Soc Encounter.
The command setPrerouteAsObs can be used to control standard cell density under power strips.But the 100% via connection from M1 to M6 under wide strip metal still block other nets' routing.I want to know how to control via generation when do special route for standcell,such as how to reserve gaps between vias for ohter net routing.thanks
 

Hi David,

Actually I did not use SOC Encounter, however in principle if you need to remove those stack vias you need to:

1 - Either return back to floorplan step, where power straps and power/ground preroute vias are dropped. Normally vias are dropped regualrly to reduce power & ground resistance, therefore maximum number of vias are dropped over power/ground nets. Therefore you need to check your floorplan scripts. They should be after horizontal & vertical power strap generation at M6 & M7

2 - If the vias to be removed are at specific regions you can delete them at any step, but before global routing of course to allow global route be aware of resources/obstructions. In this case as you'll increase the power/ground resistance you should confirm this methods validity by IR Drop analysis.

3 - If IRDrop is an issue, another option would be placing standard cell placement percentage blockages (Magma has percentage blockages which is good at reducing blockages). This is the safest method as you don't need to delete those stacked M1-to-M5 vias anymore. However as you'll need to reduce placement density this will cost you some unused area!

I'm sorry that I can not provide you commands for SOC Encounter, however there should be similar commands as Magma & ICC.

Best regards,
Gokhan
---
 
Last edited:

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top