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That was our initial thinking too.
Unfortunately client does not want to compromise signal due to reasons X,Y and Z. The design is unfortunately a joint effort between us and our client. Those kind of joint efforts are always difficult to manage since client side designers and contracted...
Yes the thick gate oxide would have been sufficient provided the client would be willing to accept the process flavor which would allow it. Our vanilla CMOS only allows for mid-oxides so we our stuck with Vgs limits of ~5V. Too many modules have been designed+tested+approved as the design has...
Thanks erikl.
Unfortunately NOT (i think). One of the process flavors would be thick-gate oxide xtors (as opposed to mid or thin oxide), however the foundry does not offer a FOXFET variant. Actually, I have never seen a process where the available transistors were of FOXFET type. What process...
I was hoping to avoid the whole [op-amp(s) driving the gate and the bulk as to respect low voltage limits]. What worries me with this approach is that capactive couplling and voltage spikes during on/off transitions will violate the low voltage limits. On top of that, it creates the need for a...
Hello all,
I am curious on what is the typical method of using a transmission gate when dealing with high voltages in processes where the Vgs_max/Vgb_max is far lower than the input/output voltage of the TG. The difficulty is in not exceeding the max Vgs/Vgb/Vgd limits. For example, an analog...
Hello all,
I am attempting to guesstimate the CMOS process used in off-shelf ICs (e.g. ADC, opamp, etc.) based on the power supply value listed in their datasheet. It usual practice not to mention it in their datasheet - they will usually mention that the IC is made in CMOS process but that is...
Thank you again for your reply and thanks for the document.
So basically, referring again to figure 2.6, when an esd event is finishing (i.e. esd current dropping towards 0A) the voltage on the pad will fall from Vh/Ih along more or less the IMAGINARY DASHED line and settle on the I-V part of...
Thank for you reply erikl.
Clarification: By "forward characteristic" do you mean the saturation (region II) or triode (region I) regions of the I-V mosfet curve ?
-Dave
Hello all,
I have a question regarding the snapback behaviors of a nmos transistor (used in esd protection).
I understand that the nmos will enter in snapback behavior when its drain will exceed Vt1 and pull back the drain voltage to ~Vhold depending on the current entering the drain.
However...
Hello all,
(I am not sure if this the correct group for this post. If not apologies to all)
I am curious if zigbee devices (802.15.4) can see wifi 802.11 wireless access points (WAN networks). I do not mean that they can talk to each other or that they transmit data to each other - I imagine...
Hello all,
(I am not sure if this the correct group for this post. If not apologies to all)
I am curious if zigbee devices (802.15.4) can see wifi 802.11 wireless access points (WAN networks). I do not mean that they can talk to each other or that they transmit data to each other - I imagine...
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