davestew
Junior Member level 1
Hello all,
I am curious on what is the typical method of using a transmission gate when dealing with high voltages in processes where the Vgs_max/Vgb_max is far lower than the input/output voltage of the TG. The difficulty is in not exceeding the max Vgs/Vgb/Vgd limits. For example, an analog sinusoidal signal ranging from 0 to 30V is fed to the input of a TG, however the maximum Vgs/Vgb/Vgd is 5V (due to the oxide thickness). The n/pmos used are the HV symetrical ones that the process offers. The maximum Vds,Vdb and Vsb is 32V of the said devices thus the drain and source voltage are ok if we do no take in consideration the -5V/+5V voltage limits on the Vgd/Vgs. I am assuming that the gate voltages will be tied to VDD/VSS to turn it on and off and the the TG is the regular textbook type (1 nmos in parrallel with 1 pmos). Changing for a cmos process where the maximum Vgs/Vds/Vgd >=30V is not an option since the design is development for some time now.
From what I can see is that the gate voltage needs to be follow min(Vd,Vs)+maxVgs_allowed in order to turn it on (for the nmos), and similarly follow min(Vd,Vs)(or lower) to turn it off. The bulk of the nmos is in a triple-well structure, so the bulk needs also to follow min(Vd,Vs). BTw, the TG can be driven by both the drain and source side so there is no easy way to tell with of the 2 d/s terminals has the lowest voltage. Is there an elegant circuit that allows to do this? well-know to all but me
Regards,
Dave
I am curious on what is the typical method of using a transmission gate when dealing with high voltages in processes where the Vgs_max/Vgb_max is far lower than the input/output voltage of the TG. The difficulty is in not exceeding the max Vgs/Vgb/Vgd limits. For example, an analog sinusoidal signal ranging from 0 to 30V is fed to the input of a TG, however the maximum Vgs/Vgb/Vgd is 5V (due to the oxide thickness). The n/pmos used are the HV symetrical ones that the process offers. The maximum Vds,Vdb and Vsb is 32V of the said devices thus the drain and source voltage are ok if we do no take in consideration the -5V/+5V voltage limits on the Vgd/Vgs. I am assuming that the gate voltages will be tied to VDD/VSS to turn it on and off and the the TG is the regular textbook type (1 nmos in parrallel with 1 pmos). Changing for a cmos process where the maximum Vgs/Vds/Vgd >=30V is not an option since the design is development for some time now.
From what I can see is that the gate voltage needs to be follow min(Vd,Vs)+maxVgs_allowed in order to turn it on (for the nmos), and similarly follow min(Vd,Vs)(or lower) to turn it off. The bulk of the nmos is in a triple-well structure, so the bulk needs also to follow min(Vd,Vs). BTw, the TG can be driven by both the drain and source side so there is no easy way to tell with of the 2 d/s terminals has the lowest voltage. Is there an elegant circuit that allows to do this? well-know to all but me
Regards,
Dave