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Recent content by datone520

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    Calibre drc error: failure to read input file stdin at record offset 0

    thanks ,but i didnot use oasis,
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    calibre PEX for postsimulation,pls

    hi frank ,lhlbluesky I encountered the same problem.whats your system ?I cannot find .stl file in my solaris 10
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    Calibre PEX errors about matching terminal and cell mapping

    Re: calibre PEX errors yes ,lVS have passed ---------- Post added at 13:10 ---------- Previous post was at 12:55 ---------- my problem is like this ,because the net name in my layout are capitals ,but in schematic ,it has small letters and capitals .just look at the pic1 and pic2 when I...
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    Calibre PEX errors about matching terminal and cell mapping

    Re: calibre PEX errors I meet the same provlems with you ---------- Post added at 04:47 ---------- Previous post was at 04:45 ---------- hi yhq0413, have you solve your problems ?could you please share your experience ?my email :lyh20041016@yahoo.com.cn
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    Calibre drc error: failure to read input file stdin at record offset 0

    Re: calibre drc error Hi lsf0201: i encontered the same problem,have you solved it?
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    ideal switch in Cadence

    hi ,all first, thanks for sharing your experience .can anyone tell me what's difference between seting open switch resistance ,close switch resistance and open voltage,closed voltage? thanks and reguard
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    problems encountered when cadence ams simulate circuits

    HI all , when I use command line cotrol cadence ams simulating ,i meet big problems . my circuits is mix signal circuits and it's spice in middle fomat.that is ,it contain two inverters ,the first one is spice netlist ,and the second is verilog module. I use command line to control the...
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    Can 10b SAR ADC with low speed achieve 9b ENOB?

    Re: 10b sar adc would you please send me some material about internal behavior of SAR ADC which i posed above ?thanks ~
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    Can 10b SAR ADC with low speed achieve 9b ENOB?

    Re: 10b sar adc HI,JoannesPaulus first ,thanks for your help ~~ why the input voltage is set to VRM,1.65V?would you please say more clearly? you can see more detail in CIC file below~
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    Can 10b SAR ADC with low speed achieve 9b ENOB?

    10b sar adc hi, JoannesPaulus thanks for your reply, you think the waveform in simulation of charge scaling dac_waveform.JPG is right??in the picture ,the input voltage is 0.65V ,reference voltage is 2V, so ,what the output of the comparator???
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    Can 10b SAR ADC with low speed achieve 9b ENOB?

    10b sar adc what i confuse above is that ,why the dac's output voltage of every step is like that? I will be waiting your answers on line all the time ~~
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    Can 10b SAR ADC with low speed achieve 9b ENOB?

    Re: 10b sar adc HI，all i dont understand why the DAC's output waveform is like the picture simulation of charge scaling dac_waveform.JPG blow。 and the structure of dac is like the picture dac_structure.JPG. I'LL appreciate it if you can give me advice.
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    Can 10b SAR ADC with low speed achieve 9b ENOB?

    10b sar adc thanks,erikl~~let me try it ~
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    Looking for materials about SAR ADC design

    SAR ADC studing~~~
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    Can 10b SAR ADC with low speed achieve 9b ENOB?

    10b sar adc so ,my simulation circuits is like sar adc simalution.JPG.i wanna get the waveform like the picture of waveform_of dac output.JPG~~how can i set the input?? can you introduce so files or papers for understanding dac output waveform??i cant understand why the differential DAC's...
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