Can 10b SAR ADC with low speed achieve 9b ENOB?

[upvl]

Hi, I'm currently working on a 10b sar adc with low speed. I use the attenuation cap in the 10b cap dac to decrease the chip size, but I'm kinda worried about the match of the unity cap and the attenuation cap, which is 32/31 of the unity cap. Actually, I don't really have to achieve 10b ENOB, so I'm OK to lose about 1-bit dynamic range. So, without calibration, can this 10b sar adc achieve 9b ENOB? Thanks.

 

[erikl]

Re: 10b sar adc

I don't know the structure of your ADC, but if you think the caps' mismatch will directly determine the resolution of your ADC's LSB(s), it is simple to calculate that their mismatch should be ≤ 1/2^ENOB , which is ≈ 0.2% in your case - and this should include the routing mismatch!

If your PDK contains process mismatch values or curves, you can calculate the min. size of your unit cap from that.

To verify if this assumption is correct, you could introduce an artificial mismatch into your schematic, simulate it and see how it affects your resolution accuracy.

 

[datone520]

10b sar adc

hi erikl,
i am working on 14 bit sar adc too ,i wanna to simulation the dac with comparator ,how would i set the input?my dac structure like this ,sorry ,i cant upload the picture.the dac structure is fully differential.any suggestions??
thanks ~~~

 

[erikl]

Re: 10b sar adc

... how would i set the input?

See **broken link removed**

 

[datone520]

Re: 10b sar adc

hi erikl ,
thanks for your help ~
but you may mistake what i mean ,i dont wanna to simulate the dnl, inl .i wanna simulate the sar adc's function ,so i simulate the whole adc ,including dac ,comparator and sar logic .now ,i wanna to see the the output waveform of DAC .and the input and output of DAC is differential .so ,how would i set the differential input in order to simulate the sar adc's function ??
any indication??I appreciate it ~~

Added after 3 minutes:

wow ,i cant upload the picture ,why ？？？if i can up load the picture ,maybe you can see the problem more clearly~
ok ,i find it !!~~

Added after 3 minutes:

 

[datone520]

Re: 10b sar adc


dac structure is like the above ~
i wanna get the dac output waveform like this :

 

[datone520]

10b sar adc

so ,my simulation circuits is like sar adc simalution.JPG.i wanna get the waveform like the picture of waveform_of dac output.JPG~~how can i set the input??
can you introduce so files or papers for understanding dac output waveform??i cant understand why the differential DAC's output waveform.
i appreciate it if you can give me more detail about the dac simulations ~

 

[erikl]

Re: 10b sar adc

... i wanna get the waveform like the picture of waveform_of dac output.JPG~~how can i set the input??

Just model the DAC inputs as PULSE (or PWL) sources as shown in the topic above. In order to create a continuous staircase, the PULSE inputs are shown there.

If you want an arbitrary series of input samples, this could get rather tedious. In this case I would create the desired analog waveform with a single PWL source, and convert it by an ideal (functional, behavorial) ADC to the proper DAC inputs.

 

[datone520]

10b sar adc

thanks,erikl~~let me try it ~

 

[datone520]

Re: 10b sar adc

HI，all
i dont understand why the DAC's output waveform is like the picture simulation of charge scaling dac_waveform.JPG blow。
and the structure of dac is like the picture dac_structure.JPG.
I'LL appreciate it if you can give me advice.

 

[datone520]

10b sar adc

what i confuse above is that ,why the dac's output voltage of every step is like that?
I will be waiting your answers on line all the time ~~

 

[JoannesPaulus]

10b sar adc

At every bit cycling step the input voltage is compared to the dac output voltage. According to the comparator's decision, at every bit cycling, the capacitors of the dac are connected to the reference VRT or VRB, scaling the dac output voltage according to the total capacitance connected to one or the other.

 

[datone520]

10b sar adc

hi, JoannesPaulus
thanks for your reply,
you think the waveform in simulation of charge scaling dac_waveform.JPG is right??in the picture ,the input voltage is 0.65V ,reference voltage is 2V, so ,what the output of the comparator???

 

[JoannesPaulus]

10b sar adc

No, the data on the slide does not correspond to the waveform shown. The input voltage is set to VRM, 1.65V.

 

[datone520]

Re: 10b sar adc

HI,JoannesPaulus
first ,thanks for your help ~~
why the input voltage is set to VRM,1.65V?would you please say more clearly?
you can see more detail in CIC file below~

 

[JoannesPaulus]

10b sar adc

It is just a picture to show the internal behavior of the adc. They probably inserted the incorrect picture or there is a typo (0.65V instead of 1.65V).

 

[datone520]

Re: 10b sar adc

It is just a picture to show the internal behavior of the adc. They probably inserted the incorrect picture or there is a typo (0.65V instead of 1.65V).

would you please send me some material about internal behavior of SAR ADC which i posed above ?thanks ~

 

[JoannesPaulus]

10b sar adc

The files you have are totally fine. The IEEExplore is also a phenomenal resource.