datone520
Junior Member level 3
HI all ,
when I use command line cotrol cadence ams simulating ,i meet big problems .
my circuits is mix signal circuits and it's spice in middle fomat.that is ,it contain two inverters ,the first one is spice netlist ,and the second is verilog module.
I use command line to control the simulation ,it comes out erros :
Error found by UltraSim in `worklib+INV_top+spice_skeleton+0x10000001', during
circuit read-in.
ERROR (SFE-23): "./.ams_spice_in/mysp.sp.sp" 8: xi2 is an instance of an
undefined model inv1.
Warning from UltraSim during hierarchy flattening.
WARNING (SFE-30): ams_internal_option_1: `addflowsuffix' is not a valid
parameter for an instance of `options'. Ignored.
SFE Parser::EDB: user time: 0:00:00 (0.080 sec), system time: 0:00:00 (0.000 sec), real time: 0:00:00 (0.090 sec)
SFE Parser::EDB: memory: 1.0483 MB total: 8.8454 MB
Error found by UltraSim.
ERROR (USIM-18610): The UltraSim simulator failed to parse the netlist.
Correct the above errors and run the simulation again.
can someone help me ??
I'll be very appreciated if you can give me some advice .
my design case is in the including file ,you download the files ,and simulate it in your own computer.
thanks~~
