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- the SRF is about 3 GHz to 4 GHz. I used Murata SMD caps, in which the datasheet claims it has low ESR value
- the ground plane is located behind the PCB (it's a double layer where the back layer acts solely as ground). The ground is also connected to copper plate and aluminium heatsink.
- I...
I use a Rogers 4350 PCB, so I think there is no big problem about PCB. Most of the SMD parts I use are of 0805 type in which I've included the non-ideal characteristic (stray inductance of the package).
What do you think about my design? Here I attach also the real PCB I made. The upper...
Hi all, I am designing a Doherty power amplifier for final project. The main amplifier is biased in class AB using NXP LDMOS BLF6G20-45 transistor.
The datasheet shows that the threshold voltage (Vth) is about 1.9 V. I biased it in 2.2V in order to go into class AB. The current at the drain is...
Need Help about Bypass Capacitor RF Power Amplifier
Hi all, I want to design a RF power amplifier using Doherty configuration. At each of the main and peak amplifier, I intend to make a bypass circuit in order to allow high-frequency go to ground (so not disturbing the power supply and output...
Hi all,
I am designing a RF power amplifier for my final project. The PA adapted Doherty architecture.
I intend to design it for input power of 25 dBm (which is 0.316 W). If the input signal is a sinusoidal signal, how much is the peak voltage?
The 25 dBm, can I consider it as a RMS value and...
Hi all, I want to simulate a power amplifier using NXP RF power transistor in Genesys. However, the NXP website only provides me with the ADS model (library) for its specific product that I want to use.
Can I somehow use this ADS model in Genesys? My version is 2009. I tried to open the NXP...
I suggest you to do "common centroid" method instead,, if you are to layout a differential pair. The topology is quiet simple :
M1 M2 M2 M1 M1 M2 M2 M1 M1 M2 M2 M1
You can extend it as much and as appropriate as possible, depending on the size of transistors you want to design.
Hope this...
Try to look at uA741 datasheet. And work on each of these parameters. Then you should be able to replace the default value of whatever op-amp in ADS it is by clicking on the value.
Hi all. I'm currently using L-Edit for course project. I try to design fully-differential folded-cascode operational amplifier with technology file of 0.18um.
However, I got difficulty in connecting the Metal1 and Metal2 with a via. I've been trying to connect them simply by via (color white)...
I currently use L-Edit for course project. I haven't tried Cadence yet, but L-Edit is quiet easy to use. The only drawback I experience is the node highlighting is not easy to use..
Thanks LvW for the solution. I figured out that circuit realizes half clock delay (z ^ -1/2). But after I tried to cascade it, the combined circuits work as a delaying unit of 1 clock (z ^ -1). Exactly what I was looking for.
Thanks again for your help..
:-D
Hi all. Is there any one knows how to realize a delaying unit (z ^ -1) functional block using switched-capacitor circuit?
Please let me know, if you know any references for it.
Thanks in advance.
:-D
Hi everyone, I need your favor.
I have to make a Zadoff-Chu implementation in C programming language. Zadoff-Chu in one part of Random Access in LTE (Long Term Evolution). Is there anyone ever do it? I need a good approach/method to start with. Please tell some reference and suggestion for this...
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