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c18 bit manipulation
I'm pretty sure using logical operations and bitmasks will compile to the proper bit-test instructions.
So for instance
"if(reg&0x08)" will compile to "btfsc reg,3" or something like that.
In the same way, I think "reg |= 0x80" will compile to "bsf reg,7"
3.3V levels *are* compatible with 5V TTL levels, but I don't know what requirements your microcontroller has (have you checked?).
I also haven't checked the IO specs of the spartan3, but one very simple way to do the conversion if the IOs are fully 5V tolerant is to use 5V pullup resistors and...
If you have a scope and pulse or step (square wave) generator you could do some simple TDR (time domain reflectormeter) measurements.
https://www.thom-tech.com/tdr.htm
Re: WRAPPER FUNCTION
Please repair your keyboard, the capslock key seems to be stuck...
A wrapper function is a pretty broad term, generally means a function which calls another function to do the real work. The wrapper function itself might change the parameters a bit, do some error checking...
Re: Analog level shifter
A voltage divider (two resistors) between +12 and the input, perhaps an opamp buffer on the output.
+12V
|
R
|
*---- OUT
|
R
|
IN
It will clamp at +/- 5V (or rather about 5.5 - 6V).
One zener is reverse biased ("zener mode") while the other is forward biased ("normal diode mode"), and vice versa...
What kind of circuit?
The short answer is yes (I've run pretty complicated things much faster on 2 layer homemade boards), but of course it depends...
If the circuit is so simple that you can route all the signals on one layer and keep the other one for a ground plane you can build pretty much...
Don't you see the FPGA itself in the JTAG chain when you run IMPACT?
I've never used the kit, but the schematic shows the FPGA along with the configuration ROM on the same chain so there shouldn't be any problem configuring the FPGA directly... I think.
Re: how the address bus related with the operating frequency
For what processor?
Some fetch and execute one instruction every clock cycle and some don't.
Some run faster internally (and have internal caches), so the *external* bus runs much slower than the cpu core.
And of course most small...
Re: Question about adder
They take up the same amount of resources in the FPGA because the full adder fits into one LUT per output bit, and you can't have less than that.
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