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For your application, you can also refer to:
A -90-dB THD rail-to-rail input opamp using a new local charge pump in CMOS
Duisters, T.A.F.; Dijkmans, E.C.;
Solid-State Circuits, IEEE Journal of
Volume 33, Issue 7, July 1998 Page(s):947 - 955
You have not checked the AC (small signal) performance of your AMP. However, your problem is related to TR (large signal) response. You can first do the settling simulation using your AMP.
Re: Gate Oxide Capacitor
When Gate oxide capacitor is used, frequency dependence should be taken into account. In your case, NWC(Gate-to-NW/N+) might be better.
Re: Post simulation on ADC
Thanks, eda4you
--Use the step response and compare it with high level models (averilog or matlab).
Actually, I am intend to confirm whether parasitic RC would impair SNDR. I cannot understand how to quarantee performance by using step repsonse ?
Re: how to simulate the startup circuit for bandgap referenc
Ramped VDD is a must in BGR simulation.
What is more, after settling, you should stop the circuit by setting STP or PDB and restart the circuit to check the function.
Post simulation on ADC
When I was designing a 60MHz 10bit Pipelined ADC, I found it tough to do a post layout simulation. The key difficulty is to get accurate FFT result.
For SRAM, ROM or Flash post simulation, I was only care about the timing delay with tolerable error up to 10%, using...
Re: about pipeline ADC!
Hi,
If your noise level and THD are lower than -80dB, there should be no problem.
Are there any problems in the options of your simulation tool?
I have never used PSS and may be I should try it.
BTW, what is your Cs, unity-gain-bw and power consumption of THA(first SHA)?
Re: Simulate DNL and INL
For 10~12bit ADC, I think simulation is tolerable.
It is no need to take 10 points per LSB, but 4 is enough to determine whether the DNL and INL is less than 0.5LSB. Such simulation (surely depends on circuit scale) is around 1~3 days if using Linux (CPU 2.8G, RAM 512M).
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