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Recent content by cmos_dude

  1. C

    I want any good material for Logical Effort concept

    Thry this book for it..... Ivan Sutherland, Bob Sproull, David Harris, "Logical Effort: Designing Fast CMOS Circuits," 1999, Morgan Kaufmann Publishers, Inc., San Francisco, CA --cmos_dude
  2. C

    Capacitor value extraction

    I could not :cry: can you please help me where can I locate it. I am using a TSMC 130nm process!!! --cmos_dude
  3. C

    Capacitor value extraction

    Hi I am doing a layout of a mim capacitor, and am getting property mismatches in the layout and source. This made me courious about the way calibre calculates the value from the layout. According to me, an mim cap value is calculated as per the expression below. Cap = C1*Area + C2*Perimeter Is...
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    Which centroid matching method is good ?

    centroid matching I agree with Ben-Ari to a lot of extent, as in small number of devices, what matters most is the interconnect parasitics. --cmos_dude
  5. C

    Netlist with top level subckt

    Im not sure about the sadence platform, but usually you need to have a symbol for the top level to have it as a subckt in your netlist. So create a symbol for the top level and then try to netlist it out. The Mentor platform provides an option to netlist it out as a subckt if you have a symbol...
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    Diff between mask layer and drawn layer

    Please correct me if I am wrong, but I gues sthere is no difference between the two. Its just two different terminologies being followed at two different levels of abstraction. For eg, a layout designer will call it as a drawn layer while a fab guy would call them as mask layers --cmos_dude
  7. C

    Help me do a layout of a mim capacitor in TSMC process

    mim capacitor Hi Thanks for your help, it will prove to be of real help. Although I still have some more queries. In my calibre deck, I see a CTM and a CBM layer for identifying the capacitor, but you have not mentioned the CBM layer. Am I missing something ??? --cmos_dude
  8. C

    substrat contact in std cell

    You can try putting them right under the VDD and VSS supply rails. That ways, you can save a lot of space!!! --cmos_dude
  9. C

    Help me do a layout of a mim capacitor in TSMC process

    Hi All I need to do a layout for a mim capacitor in a TSMC process. Can anybody help me out with it. Please be specific about all the marker layers required for the layout. Also if possible, please provide with a snapshot of the layout of a mim cap. I have no idea how it looks as I have never...
  10. C

    Rds of the MOS component

    both if possible!!!!
  11. C

    Question about silicide and non-silicide sheet resistance

    Re: about silicide The resistance of a salicided area is less than that of the non salicided part. This might be a bit confusing if you are a layout engineer and have been using salicide layers during your work. The salicide layer that you add during layouts is a negative mask (better known...
  12. C

    finger number and multiply value?

    The multiplier value is added to estimate the parasitics that will occur during layout. It is not necessary to mach the multiplier value in the schematic to the number of fingers in the layout (your Layout will still be LVS clean) but the parasitic estimates might change. If you are a layout...
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    what is the next Hot IP ?

    Its got to be Wireless USB
  14. C

    Salicide error while doing DRC with Calibre

    Re: Salicide Error Salicide is used to increase the resistance. I am aware of the use of Salicide (or for that matter salicide blockage as pointed by k_90, because Salicide is a negative mask as provided by the foundries) in layouts of ESD protection devices. The salicide is not added onto the...
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    When do we draw NFET on the p-well and when on the n-well in the layout?

    NFET in the layout An NFET in an NWELL is used to have Capacitors in the layouts. Such MOSCAPS are used because the have less fringing effects and also high Cap when compared to an MIM cap --cmos_dude
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