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Re: Help me !! saving received data >>> Sram (veril
Problem in port mapping of the SRAM instantiation.
MEM_SRAM u0(.Data_Bus(Data_Bus), .Address(Address), .nRD(nRD),
.nWR(nWR), .nCE(nCE), .Address_In(Address_In), .Data_In(Data_In),.LED(LED),.WE(WE));
data_in should be mapped to RxD_data or...
xilinx ibis
We are using xc3s400,fg456,-4 device with some pins declared with DCI option.
We generated an IBIS model from ISE for signal intergrity analysis.
In the IBIS model, the DCI pins are assigned with a model name LVDCI_33_50ohm_O / LVDCI_33_50ohm.
understanding here is the modle got...
Gate lavel simulation
I want to do gate level simulation for a design. i got netlist file and SDF file for the design.
can any body help me how to do it in VCS or NC sim.
Thanks in advance.
-Keshav
simulation tool for switches
I want to do gate level simulation for a design. i got netlist file and SDF file for the design.
can any body help me how to do it in VCS or NC sim.
Thanks in advance.
-Keshav
set up and hold time violations
Thanks for the reply,
It would of great help if you explain with a setup and hold violation example, where by changing frequency we can avoid setup violations , whereas the same is not possible with hold violation elimanation.
hold time violation
Hi,
Can any body tell me why holdtime violations will not get affected with change in frequency. But setup time violations will depend on the frequency.
Please explain me the relation of setup time/ hold time with frequency.
- Thanks
The design should be targetted to that particular device. i.e
project properties should reflect the exact spartan device.
In simple words part selected in the ISE tool should be same as that of the actual one on the board.
-Keshav
Re: Xilinix 6.1i needed
Hi,
It is available in xilinx site only.
ISE™ Classics provides a FREE collection of previously released ISE software tools.
check this link
**broken link removed**
Regards,
Keshava
Re: Verilog question
There is a difference in using ! and ~... let us take an example,like
when we want to check the condition like
-- if!(a==b) here we are validating the condition with true or false.
-- ~(a) will invert the bits of a . here a is a vector...
Re: relacing 5V TTL tolerant FPGA with 3.3V TTL I/O tolerant
you have to go for respin of the board. it u want to use 5v with the new layout also , then use level translators at FPGA I/o's. But It will increase the BOM cost of the board.
- Keshav
Hi,
There are different possibilities here like,
- If both clocks are derived from same source and both are in phase, u need not to synchronize.
- If both clocks are same and with fixed phase shift, then u need not synchronize
- If source clock is faster than the...
Hi,
Can any one tell, What is exactly 40-nm or 60-nm or 90-nm technology w.r.t to FPGA.
pls share any links related to this.
Keshav
Added after 39 minutes:
Hey Guys,
i could able to find the answer in this site. sorry for posting once again.
for the people who want to know the...
programming spartan xc3s250e
Try to connect your board with starter kit in a daisy chain fashion.
other optioni is to make a parallel cable.
Check this link
-Keshav
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