Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Verilog question - "(!resetn)" , "(~resetn)&q

Status
Not open for further replies.

SweetMusic

Newbie level 6
Joined
Nov 27, 2008
Messages
14
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,283
Activity points
1,344
Verilog question

Hello
I have one stoopid question: in verilog "(!resetn)" means the same thing with "(~resetn)" ? :D
and one more: reg[3] <= ~|d , where d in a 8 bits register ?
thank you
 

Re: Verilog question

There is a difference in using ! and ~... let us take an example,like

when we want to check the condition like

-- if!(a==b) here we are validating the condition with true or false.


-- ~(a) will invert the bits of a . here a is a vector.

hope this is clear


- Keshav
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top