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The problem with all capacitive-based startup circuits is that it's not robust.
You may have to simulate not only slow startups, but also brownout conditions.
It may give a lot of headache if you have very strict criteria on your bandgap startup.
If you need precision, you can string a bank of peak detectors in parallel.
https://en.wikipedia.org/wiki/Precision_rectifier
If precision is not required, and you can roll your own opamp, you could design an opamp with 16 +ve input terminals and get a lousy peak detector.
You have already answered your own question.
The main consideration is the error that you will see at the output when non-ideal circuits are used.
This error has various components
1. Input common-mode variation
2. Input-referred offset
3. Gain error, which is derived from feedback network...
The diode is called a body diode. It is inseparable from the MOSFET by construction.
A NMOS is constructed with n+ diffusion on p-sub.
For discrete NFETs, the p-sub is usually connected to the source, but that still leaves a p-n junction from p-sub to drain diffusion.
That's your body diode.
To the simulator, as long as vdsat=Vgs-Vth<0, they will flag the MOS as operating in region 3, and defines it as the sub-threshold region. It's stupid.
In reality, the region of vdsat<0 actually comprises of the week inversion region (sub-threshold), and part of the moderate inversion region...
If you feel that learning a new tool is boring, then there are many more stuffs in a design engineer's job that is way worse.
And to answer your question, I was never sent for any professional courses to learn the tools that I use, with one exception, and that I was already relatively...
It's pointless harping on when Node A is higher than Vth.
It will only be so if some parasitic cap stores some charges to generate a greater than Vth voltage.
The question comes with how these charges actually accumulate on Node A? Capacitive coupling? Leakage currents? Some nearby wire...
That's a +/-10% current error. That does not qualify as "relatively good".
Do a dcop on the worst MC run, and check the operating modes for all the FETs.
Also, it will be useful to provide your testbench.
I don't know what schematics you are looking at, but it's pretty much a useless structure.
Node A is a high impedance node, aka a floating input.
On power up, the voltage would depend on the capacitive divider of any parasitic caps on that node.
Run a switching signal over this line and all...
You have to get your terminology right first.
Assume you start off with an ideal single-pole opamp with open loop DC gain of 1000, and open loop -3dB frequency of 1kHz.
This gives you a gain bandwidth product of 1MHz.
You take this opamp, configure it with unity beta and you get a closed loop...
In fully differential amplifiers, what you see is a current source feeding the current sink.
It is impossible to have both currents exactly the same, and whoever "wins" will likely push the other one out of saturation.
The CMFB essentially makes one of the them adaptive to the output voltage...
Buck is a step down.
Boost is a step up.
The buck-boost is just a combination of the 2, with more complicated control control and more power FETs.
In other words, it depends on what output voltage you want and what input voltages you have available.
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