Zero current startup circuit in low power Bandgap

[she_long]

It's a normal zero current startup circuit I think, and I want to use it in a low power Bandgap.
But someone told there's startup risk in real chip. Can anybody tell the detail analysis and how to simulate it.

 

[erikl]

I think it's not a risk as long as the startUp cap is larger than the other 2 caps in the circuit (incl. their parallel parasitics). I.e. the startUp current must flow at least as long until the nodes with delay caps are settled into a stable OP.

To verify a safe startUp, I'd recommend to use a very slowly rising power supply up to the order of 100ms.

 

[checkmate]

The problem with all capacitive-based startup circuits is that it's not robust.
You may have to simulate not only slow startups, but also brownout conditions.
It may give a lot of headache if you have very strict criteria on your bandgap startup.

 

[leo_o2]

I agree with checkmate. Sometimes it failed for real silicon.