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For power isolation, I need to insert power-cut cell in my design.
I used "PDIODE8W" in my I/O library for different voltage levels isolation between digital and analog domain. There are two pins inside this power-cut cell, VSS1 and VSS2.
So, when I use the command "InsertPad", how should I...
For power isolation, I need to insert power-cut cell in my design.
I used "PDIODE8W" in my I/O library for different voltage levels isolation between digital and analog domain. There are two pins inside this power-cut cell, VSS1 and VSS2.
So, when I use the command "InsertPad", how should I...
Re: Help!How to ensure the netlists from synthesis are corre
I have specified clock in DC, and my reset is on falling edge, while clock is on rising edge.
I tried what tariq said, synthesized one module and let others remain unsynthesized.When I simulated just the synthesized module, it's OK...
Re: Help!How to ensure the netlists from synthesis are corre
to shumws,
When SDF file is spilt out, there is no warning or error, just a information says "load delay is included in cell delays".
I watch the waveform and find that just about one cycle after the reset signal, many nets return to...
Re: Help!How to ensure the netlists from synthesis are corre
Formal Logic Equivalent Check (LEC), you mean this? I didn't do that.
what is the tool for LEC? I only have the DC for synthesis and ModelSim for simulation.
the metastability , i mean X.
I synthesize my code by DC, after that, I get the netlist and SDF files. To ensure the result is correct, I use them to do a simulation, but I get no wave there except many metastabilities.
By the way, there is no timing violation after synthesis and only have one warning:" Potential...
thanks, jay.
I afraid that all these control signals in my design are of different freq, they are even not periodic strictly.
I realized I have to modify my HDL codes and improve these control signals to make my design a synchronous system.
thanks again!
Thank you guys, but I still have query.
In my design, there are many this kind of control signals, which are linked to a DFF's CK pin. so, as you said, they will all be treated as clocks. Therefore, this is a multi-asynchronous clock design.
I learned from a paper that Only allow one clock per...
Here is an example:
always@(posedge clk or negedge reset)
...
always@(posedge EN or negedge reset)
...
clk is the system clock, and EN is another control signal linked to DFF's CK pin.
when synthesis, how to constrain this module?
Should the EN be treated as an another clock, because it is...
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