Help: A question about synthesis

[cheat0821]

Here is an example:

always@(posedge clk or negedge reset)
...
always@(posedge EN or negedge reset)
...

clk is the system clock, and EN is another control signal linked to DFF's CK pin.
when synthesis, how to constrain this module?
Should the EN be treated as an another clock, because it is linked to DFF's CK pin?

Thanks a lot!

 

[jaydip]

yupp .. whats in a name ... EN or clk or clock .. you will have to treat it as an another clock ..

 

[sandy_711]

The moment you put posedge/negedge it should be considered as a clock (Assuming it is not a reset signal).

 

[cheat0821]

Thank you guys, but I still have query.
In my design, there are many this kind of control signals, which are linked to a DFF's CK pin. so, as you said, they will all be treated as clocks. Therefore, this is a multi-asynchronous clock design.
I learned from a paper that Only allow one clock per module, and Create a synchronizer module for each set of signals that pass from just one clock domain into another clock domain. So my design has to be completely re-partitioned.
My problem is that there will be too many modules after re-partition, my design is not a big one, you know, i thank it is too trivial.
Is there a better way for my design? And if not, how the constraints will be added to those new clocks?(I mean those control signals,although linked to DFF's CK pin,some are internal-generated.)

Appreciate your help.
Best regards

 

[jaydip]

if freq of that bloth clock (clk & EN) are same, use only one clock and constraint it from top level port ..

how many clocks do you have in your design?? are they all of different freq ?? if no of clocks are more than 5, serious problem with your design ..

 

[cheat0821]

thanks, jay.
I afraid that all these control signals in my design are of different freq, they are even not periodic strictly.
I realized I have to modify my HDL codes and improve these control signals to make my design a synchronous system.

thanks again!