Help!How to ensure the netlists from synthesis are correct?

[cheat0821]

I synthesize my code by DC, after that, I get the netlist and SDF files. To ensure the result is correct, I use them to do a simulation, but I get no wave there except many metastabilities.

By the way, there is no timing violation after synthesis and only have one warning:" Potential simulation-synthesis mismatch if index exceeds size of array 'Cout'". I think that is because I need a 216-bits output "Cout", which is consist of 36 6-bits units,so I use a 6-bits address from"000000" to "100011".

Why the result of simulation is wrong? just because of this warning?
What should I do next?

Thank you
Best regards

 

[shumws]

Did you LEC your netlist to check it is logically equivalent to your rtl code?

Do you mean X or Z in simulation when you say metastabilities?

 

[cheat0821]

Re: Help!How to ensure the netlists from synthesis are corre

Formal Logic Equivalent Check (LEC), you mean this? I didn't do that.
what is the tool for LEC? I only have the DC for synthesis and ModelSim for simulation.

the metastability , i mean X.

 

[shumws]

LEC is a cadence conformal tool that perform logic equivalent check

Sometime DC may spill out junks that doesn't match your rtl

For the X's that you get, do you know when does it start (e.g. starting from a state machine or all registers turn X once get out of POR or you have highZ input to some cells)

When DC spill out your SDF file, did you just look at the log and check if there are any timing violation? What happen if you do not annotate your SDF file?

I don't think " Potential simulation-synthesis mismatch if index exceeds size of array 'Cout'" is a problem if you use a signal to address your register bank.

 

[tariq786]

Do synthesis incrementally. That is synthesize one module while let others remain in the behavioral or unsynthesized state. Now run simulation and see it works.Then synthesize the second module and see if it works until all modules are synthesized. This way you will identify module that is causing problem after synthesis.

Hope it helps

 

[cheat0821]

Re: Help!How to ensure the netlists from synthesis are corre

to shumws,
When SDF file is spilt out, there is no warning or error, just a information says "load delay is included in cell delays".
I watch the waveform and find that just about one cycle after the reset signal, many nets return to X again. And if not annotate SDF file, there will be error like this:
"Error: /home/..../smic18m.v(9755): $hold( posedge CK:4 ns, posedge RN:4 ns, 500 ps); Time: 4ns Iteration: 2 Instance: /Test_Calibration/FA/F8/\Cout_reg[29][3]\". all the errors are about holdtime.
if annotate SDF file, errors still there and setuptime error ,too.
Why dose this happen? DC reports there is no timing violation, why the simulator reports so many setup and hold errors?

and to tariq,
I will try what you said, thanks for your suggestion.

Thank you, guys. I really appreciate your help!

 

[shumws]

There could be couple reasons. When you use DC, did you specify the clocks that you use? If you did not specified the clocks, It could be a problem.

Did you also buffered up the signal that address your register bank? Seems like it is a high fan out net.

Is your clock and reset on the same edge? The hold can be a reset hold time (removal) violation. If so, make your reset signal 5ns apart the clock edge.

 

[cheat0821]

Re: Help!How to ensure the netlists from synthesis are corre

I have specified clock in DC, and my reset is on falling edge, while clock is on rising edge.
I tried what tariq said, synthesized one module and let others remain unsynthesized.When I simulated just the synthesized module, it's OK. But when I do a simulation with the synthesized one and other unsynthesized modules together, there is X state again.

so, maybe it's the second reason you said. But I have already use the command "set_fix_multiple_port_nets -buffer_constants -all", and what to do next?:?: