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Recent content by chaitanya.531

  1. C

    [SOLVED] HDL Synthesis failed but got correct simulation and no syntax error

    hi folks i getting hdl synthesis error but i get expected results xilinx version 10.1 ise simulator i want to write vhdl behavioral code for 7495 shift register with operation syntax correct but following error in synthesis and by code is -------- library IEEE; use...
  2. C

    the following signal(s) form a combinatorial loop: waring

    hi plz help when i synthesis vhdl the following warnings occurs Loading device for application Rf_Device from file '4vfx12.nph' in environment C:\Xilinx. WARNING:Xst:2170 - Unit rc5round : the following signal(s) form a combinatorial loop: rc5round_ao<15>_cyo, ao<32>, rc5round_ao<30>_cyo...
  3. C

    modulo addition implementation in vhdl

    i want to do addition modulo n on integers a and b
  4. C

    modulo addition implementation in vhdl

    excuse me folks i have q about addition modulo n implementation in vhdl how do i implement that in vhdl
  5. C

    [SOLVED] Line 41. parse error, unexpected PORT, expecting OPENPAR or TICK or LSQBRACK

    thank u problem solved
  6. C

    [SOLVED] Line 41. parse error, unexpected PORT, expecting OPENPAR or TICK or LSQBRACK

    Hey Folks, plz Need a little help here with my VHDL code. I'm new to VHDL so please bear with me. I'm getting the following Error messages for my code posted below. (I'm using the xilinx 8.1.03i and modelsim ) ERROR:HDLParsers:164 - "C:/Xilinx/rcc3/fgh/rc5final.vhd" Line 41. parse error...
  7. C

    [SOLVED] HDLParsers:164 - Line 81. parse error, unexpected IDENT expecting SEMICOLON

    error rectified thank u
  8. C

    [SOLVED] HDLParsers:164 - Line 81. parse error, unexpected IDENT expecting SEMICOLON

    Hey Folks, plz Need a little help here with my VHDL code. I'm new to VHDL so please bear with me. I'm getting the following Error messages for my code posted below. (I'm using the xilinx 8.1.03i and modelsim ) ERROR:HDLParsers:164 - "C:/Xilinx/rcc3/fgh/test.vhd" Line 81. parse error...
  9. C

    [SOLVED] WARNING:Xst:2170 - Unit the following signal(s) form a combinatorial loop:

    hi plz help when i synthesis vhdl the following warnings occurs WARNING:Xst:2170 - Unit rc5round : the following signal(s) form a combinatorial loop: rc5round_ao<8>_cyo, ao<17>, c1/N27, m2<17>, rc5round_ao<5>_cyo, rc5round_ao<12>_cyo, rc5round_ao<1>_cyo, rc5round_ao<4>_cyo, m3<0>...
  10. C

    various error in programming with vhdl

    ya i get it when i synthisis following warring occurs WARNING:Xst:819 - "C:/Xilinx/rcc2/fg/rc5round.vhd" line 55: The following signals are missing in the process sensitivity list: WARNING:Xst:819 - "C:/Xilinx/rcc2/fg/mux2b1.vhd" line 18: The following signals are missing in the process...
  11. C

    various error in programming with vhdl

    plz Need a little help here with my VHDL code. I'm new to VHDL so please bear with me. I'm getting the following Error messages for my code posted below. (I'm using the xilinx 8.1.03i and modelsim ) When I run check syntax, the following is displayed eRROR:HDLParsers:164 -...
  12. C

    [SOLVED] ERROR:HDLParsers:164 " Line 38. parse error,

    ya igot thank u
  13. C

    [SOLVED] ERROR:HDLParsers:164 " Line 38. parse error,

    Hey Folks, plz Need a little help here with my VHDL code. I'm new to VHDL so please bear with me. I'm getting the following Error messages for my code posted below. (I'm using the xilinx 8.1.03i and modelsim ) When I run check syntax, the following is displayed: Compiling vhdl file...
  14. C

    please check this problem no erroprs not getting results

    ya i check the code code error i rectified thank u
  15. C

    please check this problem no erroprs not getting results

    plz check this code this give no errors on xilinx but results showing uuuuuu or xxxxxx THIS IS TEST BENCH OF A PROGRAM DECRYPTION library IEEE; use IEEE.STD_LOGIC_1164.all; use STD.TEXTIO.all; use IEEE.STD_LOGIC_TEXTIO.all; entity RC5_DECRYPT_TB is generic ( T : time := 10...
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