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Hi, all
I want to use altera stratix II FPGA as an LVDS receiver/transmiter in my design, who could supply some reference design on board level, thanks in advance.
concept hdl tutorial
Concept HDL is from former cadence, match with allegro
Capture CIS is from former orcad, match with orcad layout
now cadence purchase orcad, so they are integrated in cadence SPB package
concept hdl
Concept HDL is from former cadence, match with allegro
Capture CIS is from former orcad, match with orcad layout
now cadence purchase orcad, so they are integrated in cadence SPB package
and many people like to use Capture CIS for schematic design and allegro for PCB layout
hex to binary vhdl
do you want to translate hex into binary in VHDL fomat?
such as assembler -> hex file -> binary in VHDL format, and then run the code in FPGA or CPLD use for debuging your microprocessor which is implemented in FPGA or CPLD??
Added after 1 minutes:
I used one c code...
1 what you used is the example_driver?
2 How do you get the "wdata_req" state? by signaltap?
3 How about the local_ready signal?
4 Do you have the DDR2 Controller IP license?
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