ddr2 controller downloading to board problem?

[verilog_always]

example_driver

hi ,

In the code I had written I am not able to get wdata_req from the ddr2 controller so it always remains in the state 1. why this is happening?Below is the driver which feds to ddr2 controller IP core and then to FPGA. In the output I am not getting the wdata_req from the ddr2 and I am not able to move another state

s0: begin
state <= (ddr2_ready)? s1:s0;
wr_req <= (ddr2_ready)? 1'b1 : 1'b0;
addr <= {19'd0,counter};
rd_req <= 1'b0;
size <= 2'b01;
end
s1: begin
wr_req <= 1'd0;
if(ddr_wdata_req)
begin
wdata <= {28'd0, counter};
counter <= counter + 4'd4;
state <= (counter == 4'd12) ? s2 : s0;
be <= 4'hf;
end
else
begin
state <= s1;
end
end

 

[adamsogood]

local_ready signal

are u targeting Xilinx chip and using MIG tools? what kind of IP you are using?

my experience is that your ddr request was not sampled by the DDR IP core.

 

[verilog_always]

I am targeting stratix II device of altera IP core

 

[cfriend]

1 what you used is the example_driver?
2 How do you get the "wdata_req" state? by signaltap?
3 How about the local_ready signal?
4 Do you have the DDR2 Controller IP license?