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Recent content by carlyou

  1. C

    [SOLVED] LVS error using IBM 90n 9LP

    You use QRC rule for LVS, It may be wrong. QRC is a extract tool. Another possibility for incomplete layout is you use a wrong PDK.
  2. C

    help needed: PA affects offset PLL integral phase noise

    To avoid pulling I select offset PLL structure. But at fractional frequency the on-chip PA deteriorates PLL IPN so much, larger power out worse IPN. At integer frequency it's OK. In open loop test the VCO performance doesn't change. If does PA affect N-divider, PFD or CP's linearity? What's the...
  3. C

    integrated inductor Q measurement

    The pad is not included in the EM simulaiton. But in the test, we have the test structure to eliminate the effect.
  4. C

    probe test for my inductor - Q value problem

    Re: Q value problem the Q simulated is got from HFSS, the lumped model is used in circuit simulation
  5. C

    probe test for my inductor - Q value problem

    Q value problem When I do a probe test for my inductor(formed by two metal layer and a via trench), it seems that the Q value is much lower than HFSS result and the L value is normal, the most critical thing is the peak Q freq shift from 4G of simulation to 1.7G of test, what will cause that...
  6. C

    integrated inductor Q measurement

    When I do a probe test for my inductor(formed by two metal layer and a via trench), it seems that the Q value is much lower than HFSS result and the L value is normal, the most critical thing is the peak Q freq shift from 4G of simulation to 1.7G of test, what will cause that? PS: the inductor...
  7. C

    What's the SPICE compatibility of a model?

    I try to discuss the SPICE compatibility of a interconnect model, but I don't konw the exact definition of SPICE compatibility? Who can tell me? 3X
  8. C

    Looking for HSPICE RF model for PA design

    help: HSPICE RF model I want to do a PA design on my PC, who can give me a RF model for HSPICE, thanks very much.
  9. C

    Is bandwidth important in CMOS power amplifier?

    I want to do a CMOS design. I have seen that if the Q of output network is small, the bandwidth becomes large. I want to know the impact of BW in a PA. the smaller Q(BW), the better performance, is it right? I also want to know the importance of the output network design in a PA? Thank you very...
  10. C

    RF power amplifier IC design

    who can give a link of "RF PA for Wireless Communications" and "RF CMOS POWER AMPLIFIER, Theory, design and Implementation", I can't find them, 3x.
  11. C

    Need help making RFIC interconnect model

    RF interconnect model Are there some useful books? Added after 2 minutes: I must add to inductor of interconnect, what should I do?
  12. C

    interconnect model of RFIC

    My techer let me to do the interconnect model for RFIC, how can I begin? If someone has experience about it, could you share with me? Thankyou very much.
  13. C

    Need help making RFIC interconnect model

    RF interconnect model My techer let me to do the interconnect model for RFIC, how can I begin? If someone has experience about it, could you share with me? Thankyou very much.
  14. C

    interconnect model for RFIC

    My techer let me to do the interconnect model for RFIC, how can I begin? If someone has experience about it, could you share with me? Thankyou very much.
  15. C

    SNR issues in pipeline ADC

    SNR in pipeline ADC Have you done the system simulation? You'd better do it to see the max snr you can get.
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