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This question is related to IO standard like TTL.
I understand that originally these standards came into existence due to the inherent nature of the those transistor type.
For example, TTL would have a certain inherent characteristics and similarly CMOS etc.
Since most of the designs happen to...
this question is regarding the use of fuses in SoC or ASIC's
I have noticed that in newer designs, the number of fuse bits are quite high. As high as 20Kb for example
I can understand fuse values being used for ramp repair etc. but I see a lot of bits being used for IP configuration (e.g. to...
In general, this is what I have seen when it comes to multiple clocks. Dont read the points in isolation as they are related to the other points
1) two clocks when generated using same PLL's will not have any drift/wander/PPM
2) for point above, they can have different phases
3) when two clocks...
Thanks. Since many of the ASIC/SoC's seem to be flip chip type, I had the same thought but being a novice in this area, I was afraid to say something stupid. In flip chip type, the constraint of wire bond is not there. Also, the connections are eventually spaced out across the die in the form of...
I am from the front end design side but I do have one question related to the ASIC PD/Backend which is related to the placement of IO pads.
Why is it necessary that the IO pads are always placed on the periphery of the die? Why we cannot place a pad, let us say, in the center of the die?
Regards,
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