placement of IO

[c70206150]

I am from the front end design side but I do have one question related to the ASIC PD/Backend which is related to the placement of IO pads.
Why is it necessary that the IO pads are always placed on the periphery of the die? Why we cannot place a pad, let us say, in the center of the die?

Regards,

 

[andre_luis]

Doesn't it seem somewhat noticeable that due to EMC issues a clearance would be also needed in the center of the die, besides the space available to lay out the pads in the middle of the chip is smaller than the space available on its periphery, in addition that, being the pads grouped together in a confined space, the task of bonding them to the package leadframes would imply in a mechanical interference in the wire filament soldering process? Furthermore, being the logic spread over a larger area, it would create greater losses and delays, not mentioning waste of a larger semiconductor area reserved to the routing channels. If the entire circuitry were arranged around the pads, there would be situations on which signals would have to turn around the pads, no-sense at all.

 

[dick_freebird]

You "can" place pads in the core, I do it all the time.
But I am not under somebody's Blessed ASIC Flow
From Which Thou Shalt Not Deviate thumb.

Many chips now use area array pads (you're not
gonna get 400+ I/Os around the periphery, at any
sensible wire or bump diameter).

But max bond wire length rules at your assembly
house (or your bare-die customer's) may dictate a
maximum-inboard-of-scribe limit, in concert with
the target package cavity; in some classes of
product (like military) you will also have die visual
inspection rules which will call out bond wires that
overfly others (a potential short if you're going to
see shock / vibe testing), you might need to use the
fine print (spec min Z-axis clearance) and a full
non-destruct bond pull to get loop height, if it's a
real thicket.

And you can get away with things for prototyping
and validation, that you wouldn't want to carry the
production risk for. So you might (say) put all the
"just for ptototype test" pads in the core, and all the
"production part I/O" about the periphery.

In the middle ground, two pad-ranks, with staggered
centers (or arranged such that the bond-flare does not
fly wires over windows "too badly") can nearly double
I/O periphery density. Done that. You can engineer
packages with two bond finger shelves, and not even
have to stagger pads - just bond the outer / lower at
min loop height, then the outer at full (just not hitting
lid) loop height. Of course plastic, you just shoot the
glop at a stamped leadframe and this is maybe not so
easy to get done (only cost me $50K NRE or so, to get
that dual shelf, ceramic LGA, ~500 pin packaged developed).

 

[ads-ee]

Flip-chip packaging doesn't restrict the I/O pads to the periphery.

 

[c70206150]

Flip-chip packaging doesn't restrict the I/O pads to the periphery.

Thanks. Since many of the ASIC/SoC's seem to be flip chip type, I had the same thought but being a novice in this area, I was afraid to say something stupid. In flip chip type, the constraint of wire bond is not there. Also, the connections are eventually spaced out across the die in the form of bump maps.

--- Updated Sep 24, 2022 ---

Doesn't it seem somewhat noticeable that due to EMC issues a clearance would be also needed in the center of the die, besides the space available to lay out the pads in the middle of the chip is smaller than the space available on its periphery, in addition that, being the pads grouped together in a confined space, the task of bonding them to the package leadframes would imply in a mechanical interference in the wire filament soldering process? Furthermore, being the logic spread over a larger area, it would create greater losses and delays, not mentioning waste of a larger semiconductor area reserved to the routing channels. If the entire circuitry were arranged around the pads, there would be situations on which signals would have to turn around the pads, no-sense at all.

Hello Andre,

I agree with all your points but in some cases, there are constraints due to this restriction. For example, let us take an example of a Hard IP that normally integrate the PADs. In such cases, one has to design a different flavor of the hard IP depending on which corner the user wants to place the IP (N-E, N-W, S-E, S-W for example). So, I was thinking of this being too restrictive in certain situations though it is not recommended as a general rule for the reasons you have mentioned above

 

[ThisIsNotSam]

I am from the front end design side but I do have one question related to the ASIC PD/Backend which is related to the placement of IO pads.
Why is it necessary that the IO pads are always placed on the periphery of the die? Why we cannot place a pad, let us say, in the center of the die?

Regards,

technically you can place an IO cell anywhere you want, but there are consequences and expectations. read about area IO vs. periphery IO to get started. then read about ESD.