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Recent content by buzkiller

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    ASIC Code to FPGA Code Conversion

    Just use Synplicity Certify with the original ASIC code (except for memories and other IP that need to be redone in Coregen)
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    A question about critical path, thanks!

    Critical path A signal in a section of combinatorial logic that limits the speed of the logic. Storage elements begin and end a critical path. The path within a design that dictates the fastest time at which an entire design can run. This path runs from the source to a sink node such that if...
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    which synthesis tool are you using?

    Amplify - really good for modular designs and floorplanning
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    What should i do after assigning the Pin Package (Spartan3)?

    About FPGA? The best way toassign pins is by using the PACE tool: **broken link removed**
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    How to increase FPGA performance ?

    For Xilinx FPGA's floorplanning gives good results - typical increase of 10-20% You may also use RPM for small critical blocks, especially if they are used in different places in your design. Physical Synthesis tools (Amplify etc) are also effective sometime and much easier to use than...
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    FPGA Design Training Course in Malaysia

    https://www.xilinx.com/support/training/asia-learning-catalog.htm
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    FPGA Design Training Course in Malaysia

    fpga designs in malaysia Insight Asia Pacific Penang +604 646 9986
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    Help me find EDIF files after synthesizing code in ISE6.2i

    ISE6.2i - EDIF?? You must use 3rd party synthesis tools to get EDIF. Why do you need EDIF ? It's just a middle step between VHDL and NGD.
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    Information about Xilinx ISE 6.3 !

    Re: X1L1NX ISE 6.3 is out SP1 for 6.3 **broken link removed**
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    what's the difference between the two xilinx constraints

    xilinx offset in before **broken link removed** BEFORE defines the relationship between data arrival and the next clock edge. For example, OFFSET IN BEFORE indicates that data will be valid at the input pin of a Xilinx device at a specified time before the next clockedge arrives at the...
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    what is source synchronous devices..??

    h**p://www.fairchildsemi.com/products/interface/appfeature/sourcesynch.html
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    Is it REALISTIC to use FPGAs for portable applications?

    Coolrunner is a good choice, runs on potatoes :)
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    How often do you use IP core generators?

    I use Xilinx Coregen as often as it's humanly possible, because it improves PAR results.
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    What is best tool to learn VHDL?

    ActiveHDL is definately better for beginner, because it contains HDL entry, Graphic entry and simulator in one package.
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    HDL Entry vs. Schematic Entry Tool?

    HDL is better because you can easily introduce new tools into your flow. Verilog is supported by more tools then VHDL, because it usually used for ASIC design.
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