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Recent content by buffalo101

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    1+3 digits BCD adder/subtracter

    Hi, I'm resuming my project of making a 4x4 bits BCD adder/subtracter. The first nibble will be either 0 (positive) / 1 (negative), followed by 3 more bits for holding 3 digits. I have some left over schematics since last time I wanted to complete this: I have a full 1 digit BCD adder with...
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    Keil + LCD 44780U display

    Hello, I am supposed to play a little with a HD44780U (LCD-II) display and this platform: http://www.cs.ucv.ro/~lemeni/Downloads/Sistem%20de%20dezvoltare.pdf A template for the C program is included here: http://www.cs.ucv.ro/~lemeni/labmicro/Lab45.zip I can't understand certain things...
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    Simulating a microcontroller

    Hello, I have a microcontrollers programming class and I want to practice at home. At school, we're using C code + Keil and have a 80C552 microcontroller. How can I simulate its running ? Thank you.
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    Xilinx modelsim problem

    I have the file X_OBUF.v under the folder Xilinx\verilog\src\simprims. Is that ok? can I include that or do I need something for VHDL ?
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    Xilinx modelsim problem

    No, I am still getting these errors: 20-30 of them. I am clueless.
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    Xilinx modelsim problem

    Thank you! I was getting errors for unisim library, I did the same compile and rename thing for it, but now it seems something else is wrong. I googled and I think it has something to do with primitives. I remembered I couldn't compile vhdl\src\primitives.mti because I don't have that file.
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    Xilinx modelsim problem

    How exactly do I compile the files ? what commands? How ?
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    Xilinx modelsim problem

    This is the error.
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    Xilinx modelsim problem

    How can I precisely do that? I've tried adding the simprim files via some menu, but it seems it didn't work.
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    Xilinx modelsim problem

    Hello everyone, I'm trying to design a BCD adder/subtracter that will output results to 2x7seg displays on a spartan board. The problem is I can't simulate its running. From what I can tell, .vhd file is generated within xilinx (simulate post-place and route model), but I get compile errors in...
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