buffalo101
Newbie level 5
Hello everyone,
I'm trying to design a BCD adder/subtracter that will output results to 2x7seg displays on a spartan board. The problem is I can't simulate its running. From what I can tell, .vhd file is generated within xilinx (simulate post-place and route model), but I get compile errors in Modelsim about simprims library.
Xilinx 9.4, modelsim 6.4. Any help is appreciated.
I'm trying to design a BCD adder/subtracter that will output results to 2x7seg displays on a spartan board. The problem is I can't simulate its running. From what I can tell, .vhd file is generated within xilinx (simulate post-place and route model), but I get compile errors in Modelsim about simprims library.
Xilinx 9.4, modelsim 6.4. Any help is appreciated.