Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by braudelk

  1. B

    Passive or active resistor in on-die Xtal circuit?

    This resistor is used to startup the osillation. Typically it can provide an appropriate operation point for later Gm stage. Maybe you should provide some detail information.
  2. B

    how to analize and simulate such a loop?

    Reduce the resistance in the figure affect not much according to the tran simulation results
  3. B

    why var-R MOS oscillate at "accurate=1" in tran. s

    As u have mentioned, "method=gear" does matters. This issue is related to the arithmetic hspice used. All tools has its limitation.
  4. B

    how to analize and simulate such a loop?

    a better performance it can achieve. The question is how to analize it? Can ring oscillator be modeled as a negtive resistor in the analysis? How to do an accurate simultion? Some note: 1.a large cap of about 200pf was added from vo to ground to compensate the loop. There is also about 30pf at...
  5. B

    how to analize and simulate such a loop?

    Strictly,it may be a ICO. The loop can be viewed as a V-I converter. Do u have any suggestion?
  6. B

    how to analize and simulate such a loop?

    It seems that ring oscillator should be modeled as a negtive resistor. However, how to do ac simulation which can indicate its performance realistically?
  7. B

    how to analize and simulate such a loop?

    Here it is. Thanks
  8. B

    how to analize and simulate such a loop?

    I have edit my post. Pls click the link. Thanks
  9. B

    how to analize and simulate such a loop?

    **broken link removed** I add ultra large resistor between vo and bias and ultra large cap between bias and ac input. Simulation results shows only a phase margin of 14 degree was achieved. However a stable loop was found in transient simulation even though a current spike was added. I can't...
  10. B

    Common-mode Voltage of OPAMP

    one of the benefits of fully differential opamp is that it can define common mode voltage for input and output independently.
  11. B

    temperature sensor design using standard CMOS process

    A temperature sensor with about 8 bits resolution digital outputs is needed. A circuit as simple as possible is appreciated. For example,chopper amp may be avoided in a PTAT bias generator if necessary. Thanks a lot!
  12. B

    node cap approximation in HSPICE

    The value of cdtot,cgtot,cbtot,cstot,cgs and cgd can be reported when doing operational point analysis using HSPICE. How do they be caculated? what is the relationship between them and how to combine these values in my node cap approximation? Thanks a lot
  13. B

    How to connect the N-bit ADC to an (N+2)-bit DAC?

    Testing ADC a better approach to test adc avoiding intergrating dac in the chip is to analysing the data from logic analyser directly. u can search a free program based on MATLAB in website,such as www.maxim.com.
  14. B

    How to connect the N-bit ADC to an (N+2)-bit DAC?

    Testing ADC That is the requirement of accuracy

Part and Inventory Search

Back
Top