how to analize and simulate such a loop?

[braudelk]

**broken link removed**

I add ultra large resistor between vo and bias and ultra large cap between
bias and ac input. Simulation results shows only a phase margin of 14 degree
was achieved. However a stable loop was found in transient simulation even
though a current spike was added.

I can't post a diagram. Pls visit it in the following address:
**broken link removed**

Thanks a lot

 

[aryajur]

Can't open it

 

[braudelk]

I have edit my post. Pls click the link.

Thanks

 

[aryajur]

It still cannot find the page. Can you just try uploading the jpg file?

 

[braudelk]

Here it is.
Thanks

 

[braudelk]

It seems that ring oscillator should be modeled as a
negtive resistor. However, how to do ac simulation
which can indicate its performance realistically?

 

[aryajur]

A very interesting circuit ! I think that since the opamp is connected so as to give a negative feedback to its input termnals, it will work as a voltage controlled oscillator. To simulate it a Transent should be run. By adjusting VCTR I think we will be controlling the supply voltage of the ring oscillator and hence its operating frequency.

 

[braudelk]

Strictly,it may be a ICO. The loop can be viewed as a V-I converter. Do u have any suggestion?

 

[aryajur]

Yes, looks like it. But I don't understand, whats the advantage of having this rather than just a single MOS with the VCTR input???

 

[braudelk]

a better performance it can achieve.
The question is how to analize it? Can ring oscillator be modeled as a negtive resistor in the analysis? How to do an accurate simultion?

Some note: 1.a large cap of about 200pf was added from vo to ground to compensate the loop. There is also about 30pf at vco power suply node.
2.all pmos transistor in this figure are cascode current source.
3.Opamp used here is single stage.

 

[aryajur]

I think since the connection of the ring oscillator to the circuit is thru the power terminals, it should not be represented as a negative resistor.

 

[frankcui]

Hi! Ho Ho, please do the .tran simulation w/O R between the inputs of opamp, and also I would like you to send these simulation results to me. According to ac analysis, the main pole should at the VO terminal, so a very large Cap connected to ground exist. To reduce the cap size, you can do a try with miller cap, but for the right side of the loop, I think this will deteriorate the psrr+, what do you think?

 

[braudelk]

Reduce the resistance in the figure affect not much according to the tran simulation results