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modelsim xe +system +verilog
Wrong forum...this should be in the PLD forum.
Modelsim XE 6.2c (released with ISE/Webpack 9.1) supported Systemverilog design-constructs (but no advanced testbench stuff, like coverage/constraints/assertions -- that requires a full Mentor SE-license +...
verilog integer size
In Verilog-2001, a Verilog "integer" is a 32-bit signed value. So it has a finite minimum and maximum range. (A Verilog "real" is a floating-point value.)
If you need more than 32-bits, you can simply declare a signed reg/wire with as many bits as you want.
reg signed...
Re: library
Those are just names that TSMC gives to its standard cell libraries.
Kind of like how Intel calls its x86_64 CPUs "Core 2 Duo", and AMD uses the name "AMD Phenom, Turion" for its x86_64 product-line.
As other people have already said, LP means 'low power', GP means 'general...
what is a flioflop ?
In normal (Primetime/Design Compiler) timing notation, a positive-hold time +X ns indicates that the flop's D-input must be held steady until +X ns after the launching clock-edge.
If the hold-time is negative -X, then the time-reference is reversed. In other words, -X...
state disgram in vhdl
I don't know about Systemverilog, but for VHDL and Verilog, there are plenty of State-diagram (graphic) editors. All of them let you enter/edit diagrams on the screen, then write-out a VHDL/Verilog RTL description.
(The Verilog version will compile in any Systemverilog...
property p_tcnst;
@(posedge clk)
$fell (variable_name) |->
##tcnst $rose (variable_name);
end property
You may already know this, but but tcnst can be a declared parameter or other compile-time constant. (it doesn't have to be a literal constant.)
parameter int blah_start = 94;
parameter int...
Yes, you can. ISE 10.1, like ISE 9.2, has full support for the Spartan-3 family (all except for a few high-capacity Spartan-3 FPGAs.) Anyway, I've used 10.1 with the 3A starter-kit, so I know there is no problem.
teaching mixed verilog/vhdl courses
This poll is for FPGA synthesis only, correct?
I'd like to see two extra choices:
1) Systemverilog
2) Altera HDL (AHDL)
And for the ancient engineers:
3) ABEL
Personally, I believe in Systemverilog ... unfortunately Xilinx ISE doesn't have it. (Altera...
difference between wire and reg in verilog
In traditional Verilog-2001, no that is illegal. Nets/wires do not allow procedural-assignments.
In Systemverilog, the definition of wire is expanded, so I think procedural-assignments are allowed.
Re: Future of e and vera
Not to worry. Just as the business/financial world still uses COBOL, an ancient computer programming language that is no longer taught in university, the ASIC/EDA-world will continue to use ABEL, Altera-HDL, e, VERA, etc.
Specman is often bundled/discounted with...
systemverilog parameter
Which simulator are you using (Questasim, VCS, or Incisive)?
Some simulators don't support the full Systemverilog language.
I'm pretty sure the argument of $size() is known at compile/elaboration time. Therefore, the output of $size() inherits the constant/static...
Wow, the FSM-coverage tool can recognize state-machines in a netlist-representation? Or does the user need to declare the state-machine ahead of time, so the tool is aware of it?
Re: Can i use Matlab(Simulink)as data source to FPGAVirtexII
So is system-generator just a co-simulation linker between Simulink and an HDL-simulator? Or does it do more (like help you write synthesizeable VHDL/Verilog code?)
Sorry, I'm just a little confused between AccelDSP and System...
length vhdl
Because it's new, Systemverilog is not as widely supported as VHDL or Verilog-2001.
You're right -- at the moment, it's mostly used for testbench/verification. But there is a synthesizeable subset of Systemverilog, so it can be used for new designs. Altera Quartus-II 8.0...
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