Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
HI ALL,
here are some simplified code of my question:
/////////
module test();
...
`include "xxx.v"
...
endmodule
module top();
...
test t0();
test t1();
test t2();
...
endmodule
/////////
what i wanna ask is that can we include different files in instant t0,t1,t2 ?
if yes, how should we set...
Hi!
Is anybody translate VHDL RTL to VERILOG RTL?
I know there is a tool called vhd2vl, but this can't help due to complex link and reference of VHDL source code.
I'm wondering that can we synthesis VHDL RTL with synopsys design-compiler and stream out in VERILOG?
The VERILOG code can be RTL of...
Hi dear all,
I'm new in AMBA and hope I can get some help here.
Currently I'm working in building an AMBA compatible bus in verilog,
my "genius" boss gives me 2 options: the first is to develop on my own with only very few assistance and very short days, second option is to translate VHDL...
hi,
there is error in your code: U = fft(w.*u)/(w1);
i guess what you mean is: U = fft(w'.*u)/(w1);
right?
value in matlab are in format double float.
signl 'u' can not have infinite precision, that means: there exist quantization error, therefor even with retangle windowing the fft floor...
EMI is electron-magnetic interference. EMI get more serious with chip process goes down. Antenna rule check is to avoid layers forms a antenna which will cause serious EMI.
Bus as said that huge buffer can cause EMI problem,... actually i don't really know how it does. Maybe someone can help us.
Generally, setup time constrain the max frequency that system can archieve. Hold time violation can be fix by back-end CAD tool, espically P&R. Setup time is what we care in design and synthesis phase.
You can shorten setup time by pipelining critical path of your designe.
hi, i think that's the situation that:
when clk=1, M4 off; a=0, M3 on, therefore net b equal to 1
=> M5 on => Qb=0 => M1 on => because W/L of M1 and M2,
a ganna tend to 0 untill next clk state.
is that right?
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
