how does this register works ?!!

[ramy_maia]

I want to use this topology to implement registers as it is appropriate for my supply voltage but i can't get how does it works
please help, any one knows how, or have seen it in a paper please submit it
Thanks in advance

 

[aslijia]

hi
as i konw, it operates as a dynamic inverter: when clk is 0, it is pre-charged, Qn=1. and when clk is 1, it is time for the circuit to propagate the Dbar.

 

[haneet]

aslijia,
how can u state it as dymanic logic when the load is not dependent on the clk for precharge.
if clk='1' then we can state that it is in evaluate phase and
when clk='0' then it will depend on the input D, but this is not the case with dynamic logic.

Do correct me if i am wrong.

 

[ramy_maia]

yes haneet, i don't think it is a dynamic logic, i found some one talking about it in his paper (IMPLEMENTATION OF A PROGRAMMABLE HIGH SPEED DIVIDER FOR A 2.4 GHZ CMOS INTEGER-N FREQUENCY SYNTHESIZER, Angel M. Gómez, João Navarro )
as follows:
An adapted version of the conventional fall edgetriggered TSPC D-FF was used at the synchronous counter. This cell has the advantage of reaching higher frequencies at the expense of power consumption. The Fig. 6 (a) depicts the D-FF connected as a divide-by-2 counter, and Fig. 6 (b), its signals during a divide-by-two operation. The dimensions of the P and N transistors have to obey several requirements to guarantee the correct operation. They are: when both transistors M1 and M2 are simultaneously on, the output a must be “high”; when both transistors M3 and M4 are simultaneously on, the output b must be “low”; and when both transistor M5 and M6 are simultaneously on, the output must be “low”.
but still can't figure why did he set these conditions :?

 

[aslijia]

haneet
you are right, so is said "operate as a dynamic circuit" but not "is a dynamic circuit". you can't find any book which discribe dynamic circuit like that.

 

[ramy_maia]

al7amd llah
i knew it, it works as ratioed logic, i'll write how it works sometime later

 

[diemilio]

**broken link removed**

diemilio

 

[quan228228]

Hi, May i ask a question?

In figure etspc2.jpg, when clk = 1, a= 0, why is b equal to 1?

Tks!

 

[blacksmith_vlsi]

Hi, May i ask a question?

In figure etspc2.jpg, when clk = 1, a= 0, why is b equal to 1?

Tks!

hi, i think that's the situation that:
when clk=1, M4 off; a=0, M3 on, therefore net b equal to 1
=> M5 on => Qb=0 => M1 on => because W/L of M1 and M2,
a ganna tend to 0 untill next clk state.
is that right?

 

[ramy_maia]

It is mainly a pseudo (mostly) nmos logic, comparing to the usual TSPC for the first stage work as nlatch so required to sample the data when the clk is high, this means that if both M1 & M2 are on M2 should take the control and force node a to be low this is done by appropriate sizing of M1 & M2
similarly 2nd stage work as pdynamic to prevent the transparency between the two latches so must predischarge the node b if the clk is high what ever the node a voltage is , i.e M4 takes control also by appropriate sizing
for the 3rd stage work as platch sample its input at low clk so if both M5 & M6 is on M6 must take control pulling Qb to low voltage

for blacksmith_vlsi, when the clk is high M4 is on not off, even if it is off this will not assure the voltage of node a to be low

i hope i am correct in my analysis if anyone has a notice please share

 

[quan228228]

hi, i think that's the situation that:
when clk=1, M4 off; a=0, M3 on, therefore net b equal to 1
=> M5 on => Qb=0 => M1 on => because W/L of M1 and M2,
a ganna tend to 0 untill next clk state.
is that right?

when clk=1, M4 off ???

 

[quan228228]

Can anyone tell me?
Tks!

 

[rakesh1234]

u can refer the kang leblesi book for cmos design it is available on
www.ebooksclub.org