Need help about translating VHDL to VERILOG with synopsys

[blacksmith_vlsi]

Hi!

Is anybody translate VHDL RTL to VERILOG RTL?
I know there is a tool called vhd2vl, but this can't help due to complex link and reference of VHDL source code.
I'm wondering that can we synthesis VHDL RTL with synopsys design-compiler and stream out in VERILOG?
The VERILOG code can be RTL of Gate-level.
Is anybody done this task before?
Please give me some help or hint~ Thanks in advance~.

 

[gliss]

After synthesis do:
write -format verilog -output netlist.v

Mod: This should be in ASIC (digital) design forum