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Hi Spoorthi,
I am not sure which book you are referring but they are right. :) Basically in VLSI Industry we use another terminology to mention these things - Unateness.
Unateness is the property for each Timing Arc. Basically, Timing Arc is a combination of Input and output pin combination...
Re: How a setup and hold time values is decided to a flipflop ?
Hi Sarang,
I got your question and I really appreciate if someone ask such questions. I can understand that from very first day you can't start using some Flipflop. There is always a way or say process to design a Flipflop known...
Okay --- Again Are you talking about the .lef file ? Tech lef files the story is same.
I would say that it will be good if you give more detail about when you are saying "Technology Libraries". It's sometime very confusing -
Please give us any file name so that we can understadn more clearly...
I am not sure when you are saking this question - At what stage are you .. Like Pre-CTS or Post Routing.
Solution can be little bit vary in both the case. As such remember - there is no set of rules which you can follow to Fix the Setup violations. Solution depends on the problem and the...
During the Parasitic Extraction, you have to opt for the Inductance extraction also. R u doing that part ?
Second thing what type of design you have have.. If it's Digital - I don't think you will get Inductance.
I am sure you are talking about the .tf files (which are Named as Technology Files). If it's correct - these are basically represent the Technology rules written for the ICC tool. With the help of this - Tool understand different Foundry specific rules , which are part of DRM (Design rule...
Hi,
I hope below 3 articles can help you.
Fix Hold and Setup time 1
**broken link removed**
Fix Hold and Setup time 3
Let me know if you need any other details.
HI,
it's hard to tell you like this because we don't know the design and after effect of any change. most of the tool have some commands or in few cases companies have their internal procedure or wrapper to find out the list of such places.
basically it's a iterative process, change the cell...
Quick reply - Metal thickness changes R and C. So RC will be changed and that is directly impact Delay of the net.
For more please see the following post.
Delay of Interconnect
Parasitic Interconnect Basics.
I would say that complete learning can't be possible. But specific topics can be learned online. If you have any experience, in the VLSI design field, then May be any of us can help you to figure out from where you can learn specific topics.
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