SDF file with primetime

[dotana]

Hi everyone,
I'm a beginer in VLSI design. Now I try to run primetime and export a standard to sdf file.
After opened primetime-shell, I run:
read_lib : import .lib file to primetime: success
set link_path: success
read_verilog: import gate-level netlist : success
write_sdf -levels 1 -no_edge_merging {cell_delays timing_checks} -version 3.0 all.sdf : export sdf : success

A part from sdf file is:

 (DELAY
    (ABSOLUTE
    (IOPATH CDN Q () (10.685))
    (IOPATH CDN QN (20.787) ()) 
    (IOPATH (posedge CP) Q (32.280) (24.171))
    (IOPATH (posedge CP) QN (32.258) (38.795))
    )   
  )
  (TIMINGCHECK
    (WIDTH (negedge CDN) (26.210))
    (WIDTH (negedge CP) (26.210))
    (WIDTH (posedge CP) (26.210))
    (REMOVAL (posedge CDN)    (COND ENABLE_E===1'b1  (posedge CP)) (24.274))
    (RECOVERY (posedge CDN)    (COND ENABLE_E===1'b1  (posedge CP)) (0.000))
    (SETUP (posedge D)    (COND ENABLE_CDN_AND_E===1'b1  (posedge CP)) (20.794))
    (SETUP (negedge D)    (COND ENABLE_CDN_AND_E===1'b1  (posedge CP)) (21.679))
    (SETUP (posedge E)    (COND ENABLE_CDN===1'b1  (posedge CP)) (16.978))
    (SETUP (negedge E)    (COND ENABLE_CDN===1'b1  (posedge CP)) (26.937))
    (HOLD (posedge D)    (COND ENABLE_CDN_AND_E===1'b1  (posedge CP)) (0.000))
    (HOLD (negedge D)    (COND ENABLE_CDN_AND_E===1'b1  (posedge CP)) (0.000))
    (HOLD (posedge E)    (COND ENABLE_CDN===1'b1  (posedge CP)) (0.000))
    (HOLD (negedge E)    (COND ENABLE_CDN===1'b1  (posedge CP)) (0.000))
  )

My question is:
1. As I know, we must have input trasistion and output load to calculate the delay from input pin to output pin (from lookup table). So in this sdf file, where is the input slew and output load to export delay ? How can I change value of them?
2. I read some document about sdf file but it isn't clear with me, can someone explain the meaning of IOPATH, SETUP, HOLD lines above, or give me a document to understand them.

Thanks.

Ps: Sorry my bad English

 

[rca]

1-
SDF contians only the delay, no slew/load info,
SPEF has the load info.
Slew is only reported by timing engine.
2-
IOPATH: input to output path, means timing needed from D to Q when CP has a rising edge.
SETUP & HOLD, is the timing constrian on this cell, to back-annotated the verliog cell model, and then the simulator could check and rise an issue if a timing is violated.

 

[rahul.achates]

SDF contains only delay information ,slew is nothing but a path delay which will be in SDF file.

LOAD capacitance is needed before place and route , after that , one a particular gate , tool know the output capacitance , and tool calculate the delay with that information and keep it in SDF file.

Rahul

 

[birdy123]

hi,

Why can't you try below post.. and other parts of this post

SDF PART1