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Recent content by billyc59

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    formality: lcell_ff cannot link to reference design dffep

    Thanks for the reply, I attempted your fix and it yielded 2 libraries: a design library and a separate technology library. The problem now is that I receive blackbox instantiations because the technology library modules now create "unread tech cell pins" Firstly, what are these pins they are...
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    formality: lcell_ff cannot link to reference design dffep

    Hi, I'm having trouble linking my design to see the reference design of dffep. These libraries are all from Altera's quartus libraries made for formal verification. My cycloneii_lcell_ff library file references lc_ff dffep and I have included dffep.v into the working library, but formality...
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    Design Vision Experts?

    it would've been nice if you could post your question along with this post.
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    Precision RTL fatal error during synthesis: array access out of bounds

    the design has an error? can't be sure.
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    Precision RTL fatal error during synthesis: array access out of bounds

    no one has any experience with this tool?
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    dc_shell and formalpro

    Thanks for your help again! I've decided to stop using design compiler at the moment as I was unable to find the correcy library files. I am currently trying to use Precision RTL with some success. I opened another thread detailing my other problem with Precision.
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    Precision RTL fatal error during synthesis: array access out of bounds

    Hi again, I'm currently using Mentor Graphics' synthesis tool "Precision RTL" to compile and output gate level netlists. I am currently running into a memory access problem with the tool. This happens during the synthesis step. the resulting log error is: # Error: Fatal error: file...
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    dc_shell and formalpro

    Synthesis tool: SYNOPSYS DESIGN COMPILER Formal Verification tool: MENTOR GRAPHICS FORMALPRO I am using the synthesis tool to generate gate level netlists. I am using the formal verification too l to verify the netlists to the RTL design. My problem is cross-compatability as the netlists...
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    dc_shell and formalpro

    hi, I'm trying to put my synopsys design compiler generated netlists through formalpro for LEC, but the netlists infer an unknown module "atbl_3" Firstly, what is it? secondly, what is the corresponding library that it appeared in? lastly, will this library be recognized by formalpro...
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    formality error: "use of undeclared identifier std_logic vector" FMR_VHDL-011

    Re: formality error: "use of undeclared identifier std_logic vector" FMR_VHDL-011 I'm doing all of those steps, including setting hdlin_warn_on_mismatch_message tabs to treat the bulk of my errors into warnings. My problem now is a binding issue. No binding exists for instance XXX1 during...
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    formality error: "use of undeclared identifier std_logic vector" FMR_VHDL-011

    Re: formality error: "use of undeclared identifier std_logic vector" FMR_VHDL-011 vhdl files: at least 300. Can formality recognize underscored numbers? Formality complained about not having the correct reference to a module that was named XXXX_2 to one named XXXX_2_0_0_0 (all generated by...
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    formality error: "use of undeclared identifier std_logic vector" FMR_VHDL-011

    Re: formality error: "use of undeclared identifier std_logic vector" FMR_VHDL-011 I'm not using a script per-se. I'm using the gui.
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    formality error: "use of undeclared identifier std_logic vector" FMR_VHDL-011

    formality error: "use of undeclared identifier std_logic vector" FMR_VHDL-011 Hi, I'm trying to load my Synopsys design compiler-generated netlists into formality and I am getting the above error. use of undeclared identifier "std_logic vector" FMR_VHDL-011 I'm very confused by this issue...
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    [SOLVED] Error: Cannot find valid synthetic library module for operator 'DIV_TC_OP'. (SYNDB-34

    thanks! it works now!
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    [SOLVED] Error: Cannot find valid synthetic library module for operator 'DIV_TC_OP'. (SYNDB-34

    Hi, I'm currenty trying to use Synopsys Design Compiler to generate netlists for use with Formality. On compilation of a specific module, I run into this issue. Error: Cannot find valid synthetic library module for operator 'DIV_TC_OP'. (SYNDB-34) The project itself is rather secretive, but...
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