billyc59
Junior Member level 1
Hi, I'm currenty trying to use Synopsys Design Compiler to generate netlists for use with Formality. On compilation of a specific module, I run into this issue.
Error: Cannot find valid synthetic library module for operator 'DIV_TC_OP'. (SYNDB-34)
The project itself is rather secretive, but I can divulge that I am using the Cyclone II FPGA and the corresponding libraries found in Quartus's eda/synopsys/dc folder
I have no idea how to solve this problem. I assume that I need a synthetic library, but I don't know where to look.
exhaustive googe searches show no reference of DIV_TC_OP
please help.
Error: Cannot find valid synthetic library module for operator 'DIV_TC_OP'. (SYNDB-34)
The project itself is rather secretive, but I can divulge that I am using the Cyclone II FPGA and the corresponding libraries found in Quartus's eda/synopsys/dc folder
I have no idea how to solve this problem. I assume that I need a synthetic library, but I don't know where to look.
exhaustive googe searches show no reference of DIV_TC_OP
please help.