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Hi,
I have a wide output bus (say 128 bits) in my design. For this bus, I need to set_output_delay only for a few bits (say 33-92)
How can I do this in a 'nice' way in the sdc ( say using a for/foreach loop). I tried a for loop but that does not work
Any help is appreciated...
Thanks,
Beo
Hi,
I have a basic query re. vg netlist and ddc files.
I am trying to verify the cells in the design vs netlist. Say I have a cell INVX8 in my design.
When I count the number of such cells in the .vg file I get a certain number, something like
% grep -r INVX8 netlist.vg | wc -l
5000
ie there...
Re: why clock inverters are preferred over clock buffers in
One basic question: Why is it important to have a 50% or uniform duty cycle for the clock...?
Thanks,
Beo
Hi Yadavvlsi,
Thanks much for the clear information. Are these diagrams taken from some book or document. Will appreciate if you can point us to the source...
I am a RTL guy and a complete newbie when it comes to PD. Can you please point to some resources to help me get started...
Thanks much,
Beo
Combinatorial circuits like adder/multipliers/crc-generators whose input and output are registered form a MC path if the combinatorial delay is greater than one clk period.
Hi,
I have a simple connection between points A and B. Lets say it has some delay 'd' due to wire resistance.
Now, can we put a buffer between A and B such that the delay can be reduced.
Thanks,
Beo
DC has a check 'set_data_check' which can be used to specify timing relation between two pins none of which is a clock.
One pin is the constrained (like data pin) and the other is relative (like a clock pin).
From your description,(... After a rising edge on pin A Pin B must remain high for a...
Yes, for FIFOs which do not have depth 2^n, you will need special Gray counters. TO understand just write 3-bit Gray code from 000 to 111, you notice that it is a reflection around the center axis. You can use this property to design a Gray code that will skip some counts so that it can still...
This design takes 9 flops+1 for pass and few gates, will a SM based design take less logic..?
It will need the same no of flops...
Will it be more readable..?
input in
reg [8:0] seq;
reg pass;
always @ (posedge clk or negedge rstn)
if (~rstn)
seq <= 'b0;
else
begin
seq <= {seq[7:0],in};
if (seq[7:0] == 11001100)
pass <= 1'b1;
end
// Add logic to deassert pass
Please post a better solution or point out if there are any corrections to this
If a source delay is specified for the parent clock, it need not be given again for the generated clock. Same for uncertainity. Not sure about the clock_transition parameters.
Also both clocks are related, else we will need to specify false_path between them.
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