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The purpose of scan chains is not to determine setup and hold violations. Scan chains are used to detect manufacturing defects. Test vectors are applied through primary inputs, shifted through scan chains and observed at primary outputs. This help in determining faulty chips. https://en.wikipedia.org/wiki/Scan_chain
The test path is just a data path without the comb logic in between the flops. So normally u dont get setup issues but many hold violations. But now as we are moving towards 32nm we are seeing both the violations.
After ur chip has been manufactured then the testing takes place on ATPG machines.
While testing the chip u need to send the data sequence to the test input and check the output sequence.
U can fix the hold violations on the test path by putting delay buffers.
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