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universal gates
Folks,
A universal gate is a gate which can implement any Boolean function without need to use any other gate type.
So,the NAND and NOR gates are universal gates.
In practice, this is advantageous since NAND and NOR gates are economical and easier to fabricate and are the...
Re: tapeout
You shall provide the GDSII file to your fab along with few more details required by fab. The semicon fab will develop mask based on your files. the mask will further developed as die and then bonding the pads and packings will make a ASIC
Maybe this could be one possible solution
read_write :
process(clock,reset)
begin
if reset = '1' then
temp_data_out <= (others => '0');
elsif rising_edge(clk) then
if rd_wr = '0' then
data <= temp_data_out;
else
temp_data_in<=data;
end if;
end if;
end process read_write;
Hi,
You can try to Implement USB controller or Bluetooth controller as a project.Maybe you can come with better architecture in terms of performance.
Also,somework related in baseband design for wireless protocol
regards,
ali
Hello all,
I would like to clarify a query.
1) Can you tell me the reason for specifiying the Delay's(Input and Output) for any entity before the synthesis is done ? What is the reason behind that?
2) Do we have any automatic insertion of buffers for the input/output port for an entity during...
Hi,
It is not neccessary that a chip should funtionaly work well in ASIC if it is proven in FPGA design.
Reason:
FPGA routing are constraint driven routing,It means it has its structure already and only we short-circuit the interconnects to make each CLB to be connected. In contrast ASIC has...
Re: Deep sub-micron tech
Deep submicron technology means,using transitoros of smaller size with faster switching rates. As we know from Moore's law the size of transistors are doubled by every year in a system,the technology has to fit those inc in transistors in small area with better...
PMOS is slower than NMOS of same size . So, if u want to have both of same speed, you need to size the pmos higher(maybe roughly 3 times). Also, The mobility of holes is greater than the electrons by approximately 2 to 3 times.
Hence the equation Wp = 2 to 3 times Wn. So, is the size of...
Xilinx PACE tool Query
Can someone write about how to use Xilinx Pace tool,I have generated an UCF file and I would like to know how to do pin assignments ?
Rgds,
ALI
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