how can I solve this problem

[complex]

hi,all
there are two blocks, block A and blocks B,block A's clock is clka, and block B's
clock is clkb. block A generates a ready signal to block B, and when block B receive the ready signal , it genetates a acknowledege signal to block A.
the question is how to realize the signal ready and acknowledge signal without delay.
thx all.

 

[test_out]

Hi, I dont know exactly what do you mean by realize the ready and acknowledge signal without delay? Delay compare to what?

First of all I think you should design the circuit that can do the function and then u can see how delay is it and try to optimise.

regards

 

[koppolu1981]

Hi,
the problem about delay is not clear.
Pls try to explain the problem clearly.

 

[hermin]

if possible try to make an illustration...a picture is worth a thousand words

 

[screw]

hi, before the block give handshake, it need at least see the ready signal's edge. If u mean is to generate ready and ack simultaneously, is it possible?

 

[tarkyss]

if as you say, i dont think it is necessory to generate a ack signal, the ack signal is useless

 

[funzero]

you can just use ready in block_a signal as ack signal in block_b
block_b_ack <= block_a_ready.

 

[arp]

if its a ready 1 bit signal then what the funzero said will be correct n u just need a buffer to do that...

 

[bajahaya]

I would suggest to use a small fifo inbetween the blocks as such both are in different speed and you can retrive from fifo.

Regards,
ALI

 

[mistry.cd]

Hi,

If you wants that request and ack signal should be sync with clock then maxim delay will be the phase difference between two clock.
So if both are in phase then the delay will be of a single clock cycle.

So the logic require two flop. one for block a and one for block b.

If you don't want to sync with clock then its just wire.

Thanks,
Chirag