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Hi, guys, I am doing 10G Serdes circuit design stuffs, I need some IEEE paper, thank you so much.
(1)Design and verification of multi-gigabit transmission channels using equalization techniques
(2) A 6.4-Gb/s CMOS SerDes core with feed-forward and decision-feedback equalization
(3)Clock Recovery...
hi AdvaRes,
at very beginning, I thougt it was VCO, but now, I think maybe it's a CML mode divider using in PLL. each block is a D filp-flop. I am not very sure.
Added after 5 minutes:
I say it is not a VCO for the reason that we have already recognized our VCO in our system. we use LC-VCO...
Actually, this structure is a kind of top new tech now, I do my IC design engineer job for 4 years and I havn't seen it before. I will appreciate you guys help.
Hi all, the attach is a basic circuit block using in pll or clock generator, maybe it's a osillator or latch or whatever, the problem is I don't know the exact detail of this circuit.If anyone knows the solution please help me .
regards
Hi all,
I am trying to run a hspice file, but error exists in output log file:
**error** no definition for 402:eval
it was called by 402:opdist
**error** unknown function definition for eval
it was called by 402:opdist
the source of error is:
opdist =...
Hi all,
I am trying to run a hspice file, but error exists in output log file:
**error** no definition for 402:eval
it was called by 402:opdist
**error** unknown function definition for eval
it was called by 402:opdist
the source of error is:
opdist =...
serdes design problem
could someone give me some advises or some study material about serdes, Iam a beginning of this and really feel confused now, thank you very much.
could someone attach the following IEEE paper for me , thank you very much.
A.Rossi and G. Fucili, “Nonredundant successive approximation register for A/D converters,” Electronics letters, Vol.32, No.12, 6th June 1996.
James L. McCreary, “Matching Properties, and Voltage and Temperature...
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