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Recent content by arunshanmugam46

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    verilog memory storage-reg

    hi all, i am implementing ldpc decoder in verilog.i am in need of storing 2304 values in memory that is required till the end of the program .How to save those values without using the command *reg[0:7]mem[0:63]*.My friend suggested bram but i am not clear with it.when i searched in net for bram...
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    xilinx bram initialisation -reg

    hi all, i am implementing ldpc decoder in verilog.i am in need of storing 2304 values in memory that is required till the end of the program .How to save those values without using the command reg[0:7]mem[0:63].My friend suggested bram but i am not clear with it.when i searched in net for bram i...
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    xilinx bram initialisation -reg

    since we are reading memory from an external data file while implementing in FPGA.............access time is high as obtained from synthesis report..
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    xilinx bram initialisation -reg

    i created a bram using xilinx core generator.i used readmem command to read the values stored in .mif file generated by core gen.The problem is that access time is high to access a single location in bram...how to reduce the access time without using readmem command ......
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    q notation for verilog

    -0.9127 + 4 = 3.0873, which is the Q1.6 2-complement value of -0.9127 is 11.000101 not 11.000110
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    q notation for verilog

    i am aware of q notation.....my doubt is how to add two Q1.6 format numbers eg:-0.8364 and -0.9127 ........ when i use 2's complement addition am getting a wrong value.......
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    q notation for verilog

    how to represent a floating point -3.3456 using q format ..... ---------- Post added at 16:19 ---------- Previous post was at 16:18 ---------- note: using Q1.6 format (1bit-integer,1bit-sign 6bit-fractional part)
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    accessing .coe file in xilinx bram-reg

    hi, i have initialised bram from external file using the following coding module bramp (clk, we, addr, din, dout); input clk; input we; input [5:0] addr; input [31:0] din; output [31:0] dout; reg [31:0] ram [0:63]; reg [31:0] dout; initial begin $readmemb("bram.mif",ram, 0, 63); end always...
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    accessing .coe file in xilinx bram-reg

    thanks a lot ..how to find the index and starting address..
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    accessing .coe file in xilinx bram-reg

    ya u are right...how to access the indexx
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    accessing .coe file in xilinx bram-reg

    i need to access each of the value in bram .coe file....how to find the address or location of each stored value... eg:if values are 3a 4d 09 4f ff in .coe file i need to operate on 1 and last values (3a and fff)how to do this...thats my doubt..
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    accessing .coe file in xilinx bram-reg

    I used bram for storing the initial llr valuesof ldpc decoder using .coe file...i need to perform operations on these stored values . so i need to access the content in the .coe file ..my que is how to access the content of the value stored in bram eg:if mem[1]=7 mem[2]=8 i need to use the mem...
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    core generator in xilinx-reg

    hi all, when i use coregen to create a block ram and synthesise the code using xilinx ise 10.1 i get the following errors: Checking expanded design ... ERROR:NgdBuild:604 - logical block 'yut' with type 'blk_mem_gen_v2_7' could not be resolved. A pin name misspelling can cause this, a...
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    accessing .coe file in xilinx bram-reg

    Hi all, I'm using the Xilinx BRAM CORE GEN to develop project on LDPC DECODER... I would like to ask if anyone knows how i can store external files(.coe file) so that my Verilog program can access the content of the file during run time. i need to access the content of the memory one by one...
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    core generator in modelsim-reg

    hi all, how to run xilinx core generator files in modelsim note: i have added xilinx core lib to modelsim......then too i get errors while simulation....
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