Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by arunragavan

  1. A

    Looking for UPF labs (including rtl, script and upf files)

    Hi friends, Is anyone have UPF labs including rtl ,script and upf files. Please send me ASAP I wanna learn low power features.. Thanks Arunragavan
  2. A

    gnuplot on capacitance Vs net load

    Hi Friends I dumped set_load constraints on all the nets from PT.. How do I gnuplot with waveform and compare with DC-T set_load files. Thanks aravind R
  3. A

    How is VLSI jobs in INDIA!!!! Has LAY-OFF started!!!!!!!!

    requirements for vlsi jobs Last friday 30thMay .. Magma fired 30 employees in bangalore office.. Is anybody know this news??
  4. A

    Problem with doing place and route using SOC Encounter

    Re: SOC Encounter Do you stiched your IO pads to your netlist..Do u have the pad instances in the netlsit? Thanks
  5. A

    Zero delay for clock tree buffers/inverters in timing report

    Timing report please get whether ideal_network applied on clk port..?
  6. A

    how to generate RAM's Physical lib?

    As far as now how u can use that VCLEF create a milkyway database and generate FRAM view and use it.. U can do place and route..But u can do drc, lvs and of course no tapeout with this free versions. Thanks Arun.
  7. A

    Flexlm license problem! Failed to open the TCP port number

    lmgrd failed to open tcp port Hi Omara007, I am not any problem with PT. But problem comes only in DC. Did you fix this problem?
  8. A

    FlexLM Error : lmgrd refused vendor name list !!

    fatal design compiler is not enabled dcsh-1 Hello All, I am also facing the same issue. Is anybody fix this problem?
  9. A

    best and better <Synthesis> tools...<<<>..

    RTLCompiler is good tool.. interm if you want EC clean netlist..
  10. A

    Synopsys. 2007.03-SP*

    yes you are true. I seen some post on deepchip on 07.03 DC has lot of bugs in seq. opto.
  11. A

    I can't install Cadence Virtuoso 5.1.4.1

    cadence virtuoso on windows hi all i want cadence virtuoso for my project pls help
  12. A

    motorola power transistor handbook

    motorola transistor handbook hello i need motorola power transistor handbook (1960) and the art of electronics by horowitz
  13. A

    request for service manual

    i need a service manual for sony cd player FH-G80 and panasonic cordless phone KX-TC1520B PLS HELP ME
  14. A

    How to initialize an array structure in verilog?

    verilog array initialization $readmemh or $readmemb is not synthesizable. u can use it for simulation purpose. how to u realize in synthesis part? u must design a simple RAM for synthesis. Aravind
  15. A

    List of companies working on IC design or semiconductors in Europe

    IC design europe there r huge IC design companies in germany and england and italy u can find amd fab in germany also. u must tell which country u focussing?

Part and Inventory Search

Back
Top