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Recent content by arnarendra

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    what does the CPRI and the SRIO mean?

    CPRI and SRIO?? CPRI stands for "Common Public Radio Interface" used as a standard interface between Radio equipment (RE) and Radio equipment controller (REC) SRIO stands for "Serial Rapid IO" which is a bus standard developed by Freescale for inter-processor communication. Now it is very...
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    positive inverter circuit

    Hi, I need a circuit which gives me an output with a reverse ramp. For eg, when input is 1V, output should be 3V and when input is 3V output should be 1V (numbers are just indicative, will adjust the value for our requirements) Thanks, Naren
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    pcb crosstalk/signal integrity analysis

    To my knowledge, knowing the theory is half the work done. If you can follow it religiously then results will be good. There are many books which talk about these things. Recently I am going through "Right the First Time" by Lee Ritchey which I feel is a very good book which talks about these...
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    how to design asynchronous read and write register

    I guess you can double clock the control signals used for read/write which will avoid the metastability problem.
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    How LDO differs from Linear regulators

    I would like to add a small point. In LDO, the difference in voltage can be low (not necessarily low always as it depends on the design). In a normal linear regulator the output voltage starts dropping when Vin comes below Vout +1V whereas in an LDO output voltage sustains till Vin = Vout +...
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    FPGA is required??????????

    FPGA stands for Field Programmable Gate Array. It is not necessary to have Xilinx board only for testing FPGA codes. It depends on which FPGA you are using. Currently you can get them from Xilinx, Altera, Lattice etc. Normally VHDL and verilog are used for developing FPGA programs. A bit of...
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    FIFO Depth when READ Frequency equal to WRITE Frequency

    Hi, To my knowledge it depends on your application, like who is writing into the FIFO and who is reading from it. How much time does it take for reading from it. If there is control over that then depth can be of your choice based on the resources available. -Naren
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    SPI question: how does the slave know the start of Byte?

    Basic SPI question Hi, I would like to make one point clear here: spi clock is NOT a free running clock. It will be clocked only when there is valid data. So, the start of the byte can always be captured with the start of the clock. I hope it clarifies it. Regards, Naren
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    Quick CoreGen question..

    Are you talking about Xilinx Coregen? If not, please ignore the response. I am not sure if frequency can be specified anywhere. When I used it, I did not specify the frequency. You need not bother to change the value if it has come.
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    Interfacing sdram controller with FPGA

    ddr sdram controller fpga DDR is a standard protocol. It should be the same for Micron and Infineon (there may be minor differences in the timing which you can verify). The DDR manufacturers will conform to the JEDEC standards, so if you ask me it should not be a problem. You just have to...
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    Interfacing sdram controller with FPGA

    sram controller on fpga I would suggest you to look for the ready code. SDRAM controller is not just programming mode registers, it involves much more than that. In your case it is DDR (Double data rate) which is little more than the SDR (single data rate). You need to take care of timing also...
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    How to understand DDR SDRAM cell bank

    Just to continue with my earlier reply, the DDR memroy chip will have internal data bus width which is twice that at the external bus. By this it manages the double data rate with 2n prefetch. It captures 16 bits on positive edge and 16 bits on negative edge. The entire 32 bits are then used...
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    Interfacing sdram controller with FPGA

    sdram fpga controller First of all to answer your question, SDRAM controller is a device (or program running in the FPGA) which generates all the required signals (control, address) for writing onto the memory or reading from it. It should also abide by the standards. The part number you have...
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    problem with wait states

    I think you will have to arrive at some condition which will define the wait duration dynamically. Other way is to delay the signals (flop them as many times as the delay is required) and use. I might be very premitive but this is what I thought.
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    Interfacing sdram controller with FPGA

    implementing dram controller in fpga SDRAM controller is the one which controls the SDRAM operations. Normally you will find it in most of the microprocessors. Microprocessor will use SDRAM to store the data for its processing and thus needs a controller. If you tell what exactly you need to...
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