FIFO Depth when READ Frequency equal to WRITE Frequency

[spartanthewarrior]

Hi All,

Can any body tell me that

What should be the FIFO Depth when READ Frequency == WRITE Frequency

 

[balan]

hi,
the depth should be one, as there is no loss of data if read and write frequency are same.


thank you

 

[quan228228]

hi,
the depth should be one, as there is no loss of data if read and write frequency are same.


thank you

although same frequency two clock domain, the depth cant be one, because the fifo should spend some clock cycle determine the fifo is full or empty like asynchronous FIFO.

 

[arnarendra]

Hi,

To my knowledge it depends on your application, like who is writing into the FIFO and who is reading from it. How much time does it take for reading from it. If there is control over that then depth can be of your choice based on the resources available.

-Naren

 

[shnain]

Hi All,

The jitter and/or drift b/w the read and write clocks can be an issue resulting in two writes before a read, so it's preferable to set the FIFO depth to at least 2.

Hope it helps!
Said.