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thevinins theorem
Can we thevinize a ckt consisting of capacitors...I read somewhere that thevinins theorem can be used for any linear ckt..
Or if somebody could explain how to solve this RC ckt belo for the final voltage across the RC load..
Thank u for ur reply grig. But the noisy digital PMOS transistors would be sharing the same n-well with the analog PMOS TXRS right?. Noise could be coupled in through the common n-well?
It is mentioned in Razavi design of AIC book pg 663 that by using PMOS differential inputs the effect of substrate noise can be reduced? I did not understand how it could achieve this more than an NMOS input could?
I believe you should connect the n-well to Vdd2 as it has a positive ripple. The n-well acts as the base of the parasitic pnp transistor and if a negative peak comes at the base -nwell- then it can switch on the pnp transistor and possibly sustain a latchup. But since the peaking in Vdd2 is...
Re: What is CMFB ??
Common Mode Feedback circuitry is used to stabilise your output dc voltage in a 2 stage OTA circuit. This is achieved by comparing your output dc level with a reference voltage level and the resulting error voltage is fed back into your first amplifier stage. This error...
Lambda ∞ (1 / L)
your lambda changes with your channel length. So the only way you can determine your lamda is from your Ids vs Vds curve by determining the slope of the curve in the saturation region
slope = dIds/ dVds = lamda*Id
And we know the Id value
Somebody please correct me if I am...
The main idea is that ur rise time and fall time of your output voltage signal are the same. And for this the resistance of the nmos and pmos should be the same. This can be achieved only by sizing the pmos 3 times to the nmos sizing.
Can we always convert a diode connected transistor to (1/gm // ro) for small signal analysis irrespective of its source voltage...? even if a resistance is connected to the src.. Am i right?
To keep the Bias current constant the Vgs has to remain the same. So the source voltage keeps up (follows) the gate voltage. This is not always true if we take into consideration the body effect - change in Vth as the Vsb not equal to 0
Could somebody please explain how the gain of a MOS differential amplifier changes with unsymmetrical input transistors.
Unsymmetric as in different W/L ratios. Usually both the input transistors have the same sizing.
I am a novice in this field. So please do bear with me if the qtn is stupid : ) ...
To increase the W/L ratio of a transistor we connect 2 transistors in parallel. if same W/L ratio's the resulting sizing would be 2(W/L). Am I right in this?
Similarly how can you achieve a increase in L sizing.
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