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to be exact, the design will be a simple processor core and a memory hierarchy. the FINAL target is to build a chip, but lots of architectural changes will have to be done in memory and the core itself to explore performance issues before starting.
in brief, we need to build a full processor...
I don't know if this is the right place to ask this question, But I will ask it anyway.
there are lots of cycle accurate simulators out there, all of them are intended for x86 architecture, some extended to be a full system simulator that could work as a virtual machine.
what if I need to write...
How to create/synthesize a power up sequence for a specific design?
Let's take for example a DDR3 memory controller. Power up or Reset initialization sequence requires asserting/deasserting multiple signals, each for a specific amount of time or requires that some signals become asserted a...
I want to make a generic Mux. not just generic in the Width of inputs, But the number of inputs too.
something like this:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
----------------------------------------
entity Mux is
generic
(
INPUT_WIDTH : integer := 8...
Sorry to use the same thread again, But if I haven't used std_logic_vector(0 downto 0) what would have been the solution?? how to assign std_logic to std_logic_vector(0 downto 0) ?
In more details again, I mean in some cases I have to use designs with generics set to only 1, resulting in a...
I always use generics in my designs, for example I use WIDTH parameter with registers to specify how many bits it can hold, This has one problem though, If I need to use WIDTH=1 (a single Flip Flop) Design Compiler complains about signal assignment (Assigning std_logic from the top design to...
There are lots of components that are really much used in designs (Muxes,Buffers, etc). rewriting them each time or copying files from project to project is nonsense.
I want to create a VHDL library and save these components in it. I've searched about this and I can't find a good reference on...
I have a component with generic.
component DCache_SinglePortRam is
generic (Width : integer := 32;
Length : integer:= 256);
port(Clk: in std_logic;
WordLine : in std_logic_vector(Length-1 downto 0);
DataIn : in std_logic_vector (Width-1 downto 0)...
I'm am trying to simulate some VHDL codes that use Synopsys Design Ware components in modelsim.
I added the Design ware vhdl files to a directory called DWARE in my work directory. I have successfully compiled some files(they include DWARE). but there is onlyone file that produces the error. All...
Is it possible to generate a Netlist form a software and use it in another ??
Can I for example generate a circuit level netlist in Xilinx ISE and then use it with Synopsys DC ??
how does Nvidia build their cache memories ??
In page 8 of this document you can see that each SMX has 32 Load/Store units. at least 16 of them are operating at a time.
http://www.nvidia.com/content/PDF/kepler/NVIDIA-Kepler-GK110-Architecture-Whitepaper.pdf
how do they build a cache memory to...
how can I multiply signed numbers in two's complement form ??
I tried the ordinary way but it seems to work only if the product is the same size with the operators
for example :
4 * -4 = -16 ======> 0000 0100 * 1111 1100 = 1111 0000 works fine
but
50 * -50 = -2500 ======> 0011 0010 * 1100...
Hi , I have an atmega8 with its clock fuses unknown !!
I want to program it but I dont know what type of oscillator to use
is there anyway to restore the fuses to original state (1 Mhz internal oscillator)???
I have a USBasp programmer only .
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